De'maris R Brown
Examiner (ID: 4353)
Most Active Art Unit | 2437 |
Art Unit(s) | CSDE, 2437 |
Total Applications | 45 |
Issued Applications | 29 |
Pending Applications | 0 |
Abandoned Applications | 16 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 4740066
[patent_doc_number] => 20080233719
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-09-25
[patent_title] => 'Method for Manufacturing Crystalline Semiconductor Film and Method for Manufacturing Thin Film Transistor'
[patent_app_type] => utility
[patent_app_number] => 12/044193
[patent_app_country] => US
[patent_app_date] => 2008-03-07
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0233/20080233719.pdf
[firstpage_image] =>[orig_patent_app_number] => 12044193
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/044193 | Method for manufacturing crystalline semiconductor film and method for manufacturing thin film transistor | Mar 6, 2008 | Issued |
Array
(
[id] => 4455614
[patent_doc_number] => 07892858
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-02-22
[patent_title] => 'Semiconductor package with stacked semiconductor die each having IPD and method of reducing mutual inductive coupling by providing selectable vertical and lateral separation between IPD'
[patent_app_type] => utility
[patent_app_number] => 12/042903
[patent_app_country] => US
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[pdf_file] => patents/07/892/07892858.pdf
[firstpage_image] =>[orig_patent_app_number] => 12042903
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/042903 | Semiconductor package with stacked semiconductor die each having IPD and method of reducing mutual inductive coupling by providing selectable vertical and lateral separation between IPD | Mar 4, 2008 | Issued |
Array
(
[id] => 5546068
[patent_doc_number] => 20090155945
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-06-18
[patent_title] => 'Method of manufacturing substrate for forming device, and method of manufacturing nitride-based semiconductor laser diode'
[patent_app_type] => utility
[patent_app_number] => 12/073293
[patent_app_country] => US
[patent_app_date] => 2008-03-04
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0155/20090155945.pdf
[firstpage_image] =>[orig_patent_app_number] => 12073293
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/073293 | Method of manufacturing substrate for forming device, and method of manufacturing nitride-based semiconductor laser diode | Mar 3, 2008 | Issued |
Array
(
[id] => 5385803
[patent_doc_number] => 20090227048
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-09-10
[patent_title] => 'METHOD FOR DIE BONDING HAVING PICK-AND-PROBING FEATURE'
[patent_app_type] => utility
[patent_app_number] => 12/042093
[patent_app_country] => US
[patent_app_date] => 2008-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 1938
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[pdf_file] => publications/A1/0227/20090227048.pdf
[firstpage_image] =>[orig_patent_app_number] => 12042093
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/042093 | METHOD FOR DIE BONDING HAVING PICK-AND-PROBING FEATURE | Mar 3, 2008 | Abandoned |
Array
(
[id] => 4673483
[patent_doc_number] => 20080211111
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-09-04
[patent_title] => 'INTEGRATED CIRCUIT PACKAGE SYSTEM WITH UNDERFILL'
[patent_app_type] => utility
[patent_app_number] => 12/037084
[patent_app_country] => US
[patent_app_date] => 2008-02-25
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0211/20080211111.pdf
[firstpage_image] =>[orig_patent_app_number] => 12037084
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/037084 | Integrated circuit package system with underfill | Feb 24, 2008 | Issued |
Array
(
[id] => 8375224
[patent_doc_number] => 08258015
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-09-04
[patent_title] => 'Integrated circuit package system with penetrable film adhesive'
[patent_app_type] => utility
[patent_app_number] => 12/035493
[patent_app_country] => US
[patent_app_date] => 2008-02-22
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12035493
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/035493 | Integrated circuit package system with penetrable film adhesive | Feb 21, 2008 | Issued |
Array
(
[id] => 4813478
[patent_doc_number] => 20080194109
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-08-14
[patent_title] => 'Method of fabricating a semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 12/071014
[patent_app_country] => US
[patent_app_date] => 2008-02-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[patent_no_of_words] => 10459
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0194/20080194109.pdf
[firstpage_image] =>[orig_patent_app_number] => 12071014
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/071014 | Method of fabricating a semiconductor device | Feb 13, 2008 | Abandoned |
Array
(
[id] => 5480240
[patent_doc_number] => 20090203197
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-08-13
[patent_title] => 'NOVEL METHOD FOR CONFORMAL PLASMA IMMERSED ION IMPLANTATION ASSISTED BY ATOMIC LAYER DEPOSITION'
[patent_app_type] => utility
[patent_app_number] => 12/028423
[patent_app_country] => US
[patent_app_date] => 2008-02-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_words] => 7129
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[pdf_file] => publications/A1/0203/20090203197.pdf
[firstpage_image] =>[orig_patent_app_number] => 12028423
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/028423 | NOVEL METHOD FOR CONFORMAL PLASMA IMMERSED ION IMPLANTATION ASSISTED BY ATOMIC LAYER DEPOSITION | Feb 7, 2008 | Abandoned |
Array
(
[id] => 5527313
[patent_doc_number] => 20090197390
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-08-06
[patent_title] => 'LOCK AND KEY STRUCTURE FOR THREE-DIMENTIONAL CHIP CONNECTION AND PROCESS THEREOF'
[patent_app_type] => utility
[patent_app_number] => 12/026843
[patent_app_country] => US
[patent_app_date] => 2008-02-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => publications/A1/0197/20090197390.pdf
[firstpage_image] =>[orig_patent_app_number] => 12026843
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/026843 | Lock and key structure for three-dimensional chip connection and process thereof | Feb 5, 2008 | Issued |
Array
(
[id] => 4845984
[patent_doc_number] => 20080182392
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-31
[patent_title] => 'Method for fabricating polysilicon layer with large and uniform grains'
[patent_app_type] => utility
[patent_app_number] => 12/011804
[patent_app_country] => US
[patent_app_date] => 2008-01-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 1966
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[pdf_file] => publications/A1/0182/20080182392.pdf
[firstpage_image] =>[orig_patent_app_number] => 12011804
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/011804 | Method for fabricating polysilicon layer with large and uniform grains | Jan 28, 2008 | Abandoned |
Array
(
[id] => 4474499
[patent_doc_number] => 07867830
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-01-11
[patent_title] => 'Manufacturing method for electronic component with sealing film'
[patent_app_type] => utility
[patent_app_number] => 12/011584
[patent_app_country] => US
[patent_app_date] => 2008-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
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[patent_no_of_words] => 8664
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[pdf_file] => patents/07/867/07867830.pdf
[firstpage_image] =>[orig_patent_app_number] => 12011584
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/011584 | Manufacturing method for electronic component with sealing film | Jan 27, 2008 | Issued |
Array
(
[id] => 4514381
[patent_doc_number] => 07910496
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-03-22
[patent_title] => 'Technique for forming an interlayer dielectric material of increased reliability above a structure including closely spaced lines'
[patent_app_type] => utility
[patent_app_number] => 12/020234
[patent_app_country] => US
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[pdf_file] => patents/07/910/07910496.pdf
[firstpage_image] =>[orig_patent_app_number] => 12020234
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/020234 | Technique for forming an interlayer dielectric material of increased reliability above a structure including closely spaced lines | Jan 24, 2008 | Issued |
Array
(
[id] => 4764079
[patent_doc_number] => 20080175290
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-24
[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 12/016386
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[patent_app_date] => 2008-01-18
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[firstpage_image] =>[orig_patent_app_number] => 12016386
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/016386 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME | Jan 17, 2008 | Abandoned |
Array
(
[id] => 4833519
[patent_doc_number] => 20080132066
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-06-05
[patent_title] => 'Integrated Circuit Having a Top Side Wafer Contact and a Method of Manufacture Therefor'
[patent_app_type] => utility
[patent_app_number] => 12/016443
[patent_app_country] => US
[patent_app_date] => 2008-01-18
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[firstpage_image] =>[orig_patent_app_number] => 12016443
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/016443 | Integrated circuit having a top side wafer contact and a method of manufacture therefor | Jan 17, 2008 | Issued |
Array
(
[id] => 5342850
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[patent_issue_date] => 2009-07-16
[patent_title] => 'Fabrication of Compact Semiconductor Packages'
[patent_app_type] => utility
[patent_app_number] => 12/014443
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 12014443
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/014443 | Fabrication of Compact Semiconductor Packages | Jan 14, 2008 | Abandoned |
Array
(
[id] => 5581022
[patent_doc_number] => 20090176368
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-07-09
[patent_title] => 'MANUFACTURING METHOD FOR AN INTEGRATED CIRCUIT STRUCTURE COMPRISING A SELECTIVELY DEPOSITED OXIDE LAYER'
[patent_app_type] => utility
[patent_app_number] => 11/970673
[patent_app_country] => US
[patent_app_date] => 2008-01-08
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/970673 | MANUFACTURING METHOD FOR AN INTEGRATED CIRCUIT STRUCTURE COMPRISING A SELECTIVELY DEPOSITED OXIDE LAYER | Jan 7, 2008 | Abandoned |
Array
(
[id] => 4778937
[patent_doc_number] => 20080286935
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-11-20
[patent_title] => 'METHOD OF FABRICATING AN ISOLATION SHALLOW TRENCH'
[patent_app_type] => utility
[patent_app_number] => 11/969913
[patent_app_country] => US
[patent_app_date] => 2008-01-06
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/969913 | Method of fabricating an isolation shallow trench | Jan 5, 2008 | Issued |
Array
(
[id] => 4752707
[patent_doc_number] => 20080160782
[patent_country] => US
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[patent_title] => 'Method for forming insulating film'
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[patent_app_number] => 12/003464
[patent_app_country] => US
[patent_app_date] => 2007-12-26
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[firstpage_image] =>[orig_patent_app_number] => 12003464
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/003464 | Method for forming insulating film | Dec 25, 2007 | Abandoned |
Array
(
[id] => 91864
[patent_doc_number] => 07736932
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-06-15
[patent_title] => 'Method of manufacturing sensor with photodiode and charge transfer transistor'
[patent_app_type] => utility
[patent_app_number] => 11/960024
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[patent_app_date] => 2007-12-19
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[firstpage_image] =>[orig_patent_app_number] => 11960024
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/960024 | Method of manufacturing sensor with photodiode and charge transfer transistor | Dec 18, 2007 | Issued |
Array
(
[id] => 4577748
[patent_doc_number] => 07833820
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-11-16
[patent_title] => 'Nanoparticle containing siloxane polymers'
[patent_app_type] => utility
[patent_app_number] => 12/000553
[patent_app_country] => US
[patent_app_date] => 2007-12-13
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[pdf_file] => patents/07/833/07833820.pdf
[firstpage_image] =>[orig_patent_app_number] => 12000553
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/000553 | Nanoparticle containing siloxane polymers | Dec 12, 2007 | Issued |