Search

Dean J. Kramer

Examiner (ID: 13130)

Most Active Art Unit
3652
Art Unit(s)
3652, 3102, 3651, 2167, 3617
Total Applications
3926
Issued Applications
3102
Pending Applications
102
Abandoned Applications
733

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19546715 [patent_doc_number] => 20240363751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => INTERFACE PROFILE CONTROL IN EPITAXIAL STRUCTURES FOR SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/771551 [patent_app_country] => US [patent_app_date] => 2024-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10090 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18771551 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/771551
INTERFACE PROFILE CONTROL IN EPITAXIAL STRUCTURES FOR SEMICONDUCTOR DEVICES Jul 11, 2024 Pending
Array ( [id] => 19560160 [patent_doc_number] => 20240371952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => BACKSIDE CONTACT STRUCTURES FOR SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/770393 [patent_app_country] => US [patent_app_date] => 2024-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10459 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18770393 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/770393
BACKSIDE CONTACT STRUCTURES FOR SEMICONDUCTOR DEVICES Jul 10, 2024 Pending
Array ( [id] => 19696609 [patent_doc_number] => 20250015154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => Multigate Device Having Reduced Contact Resistivity [patent_app_type] => utility [patent_app_number] => 18/769940 [patent_app_country] => US [patent_app_date] => 2024-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13836 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18769940 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/769940
Multigate device having reduced contact resistivity Jul 10, 2024 Issued
Array ( [id] => 19634772 [patent_doc_number] => 20240413221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => INTEGRATED CIRCUIT DEVICE WITH IMPROVED RELIABILITY [patent_app_type] => utility [patent_app_number] => 18/770408 [patent_app_country] => US [patent_app_date] => 2024-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11835 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18770408 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/770408
INTEGRATED CIRCUIT DEVICE WITH IMPROVED RELIABILITY Jul 10, 2024 Pending
Array ( [id] => 20361748 [patent_doc_number] => 12477766 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-18 [patent_title] => Semiconductor transistor device structure including nanostructure and gate structure with protection layer and fill layer and method for forming the same [patent_app_type] => utility [patent_app_number] => 18/769168 [patent_app_country] => US [patent_app_date] => 2024-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 50 [patent_no_of_words] => 4430 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18769168 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/769168
Semiconductor transistor device structure including nanostructure and gate structure with protection layer and fill layer and method for forming the same Jul 9, 2024 Issued
Array ( [id] => 19546590 [patent_doc_number] => 20240363626 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => Self-Aligned Etch in Semiconductor Devices [patent_app_type] => utility [patent_app_number] => 18/766867 [patent_app_country] => US [patent_app_date] => 2024-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17222 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18766867 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/766867
Semiconductor transistor devices having double-sided interconnect structures Jul 8, 2024 Issued
Array ( [id] => 20334510 [patent_doc_number] => 12464806 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Semiconductor transistor device having backside source/drain contact with a low-k spacer and method of forming the same [patent_app_type] => utility [patent_app_number] => 18/766991 [patent_app_country] => US [patent_app_date] => 2024-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 5559 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18766991 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/766991
Semiconductor transistor device having backside source/drain contact with a low-k spacer and method of forming the same Jul 8, 2024 Issued
Array ( [id] => 19531984 [patent_doc_number] => 20240355886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => SEMICONDUCTOR DEVICE HAVING A JUNCTION PORTION CONTACTING A SCHOTTKY METAL [patent_app_type] => utility [patent_app_number] => 18/760960 [patent_app_country] => US [patent_app_date] => 2024-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5755 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18760960 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/760960
Semiconductor device having a junction portion contacting a Schottky metal Jun 30, 2024 Issued
Array ( [id] => 20119623 [patent_doc_number] => 12369362 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => Forming semiconductor structures with two-dimensional materials [patent_app_type] => utility [patent_app_number] => 18/759611 [patent_app_country] => US [patent_app_date] => 2024-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 8 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18759611 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/759611
Forming semiconductor structures with two-dimensional materials Jun 27, 2024 Issued
Array ( [id] => 20347615 [patent_doc_number] => 12471353 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Gate-all around transistor with isolating feature under source/drain [patent_app_type] => utility [patent_app_number] => 18/759037 [patent_app_country] => US [patent_app_date] => 2024-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 50 [patent_no_of_words] => 5853 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18759037 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/759037
Gate-all around transistor with isolating feature under source/drain Jun 27, 2024 Issued
Array ( [id] => 19515938 [patent_doc_number] => 20240347624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => Inner Spacer Liner [patent_app_type] => utility [patent_app_number] => 18/753469 [patent_app_country] => US [patent_app_date] => 2024-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8760 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18753469 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/753469
Gate-all-around transistor having inner space lined by a semiconductor liner and method of forming the same Jun 24, 2024 Issued
Array ( [id] => 20553231 [patent_doc_number] => 12564045 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-24 [patent_title] => Semiconductor device structure with interconnect structure having air gap [patent_app_type] => utility [patent_app_number] => 18/751628 [patent_app_country] => US [patent_app_date] => 2024-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 1202 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18751628 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/751628
Semiconductor device structure with interconnect structure having air gap Jun 23, 2024 Issued
Array ( [id] => 19500432 [patent_doc_number] => 20240339450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT DEVICE [patent_app_type] => utility [patent_app_number] => 18/746928 [patent_app_country] => US [patent_app_date] => 2024-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16296 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18746928 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/746928
Integrated circuit device including N-channel metal-oxide semiconductor (NMOS) transistor region and a P-channel metal-oxide semiconductor (PMOS) transistor region Jun 17, 2024 Issued
Array ( [id] => 19500479 [patent_doc_number] => 20240339497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => Dual Side Contact Structures in Semiconductor Devices [patent_app_type] => utility [patent_app_number] => 18/747151 [patent_app_country] => US [patent_app_date] => 2024-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7590 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18747151 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/747151
Dual side source/drain contact structures in semiconductor devices and method for forming the same Jun 17, 2024 Issued
Array ( [id] => 20531911 [patent_doc_number] => 12550362 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Transistor device with tapered gate contact profile [patent_app_type] => utility [patent_app_number] => 18/737382 [patent_app_country] => US [patent_app_date] => 2024-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 49 [patent_no_of_words] => 11378 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18737382 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/737382
Transistor device with tapered gate contact profile Jun 6, 2024 Issued
Array ( [id] => 19468265 [patent_doc_number] => 20240321935 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/732363 [patent_app_country] => US [patent_app_date] => 2024-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9545 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18732363 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/732363
Display device including an optical sensor on an area overlapping an active area of a display panel Jun 2, 2024 Issued
Array ( [id] => 19468220 [patent_doc_number] => 20240321890 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => FIN FIELD-EFFECT TRANSISTOR AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/673632 [patent_app_country] => US [patent_app_date] => 2024-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12602 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18673632 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/673632
Multiple back side/buried power rail (BPR) cell including field-effect transistors with air void between two adjacent BPR cells May 23, 2024 Issued
Array ( [id] => 20245979 [patent_doc_number] => 12426324 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Gates structures of nanostructure field-effect transistors (nano-FETs) including a plurality of semiconductor based capping materials and methods of forming the same [patent_app_type] => utility [patent_app_number] => 18/673998 [patent_app_country] => US [patent_app_date] => 2024-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 46 [patent_no_of_words] => 6795 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18673998 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/673998
Gates structures of nanostructure field-effect transistors (nano-FETs) including a plurality of semiconductor based capping materials and methods of forming the same May 23, 2024 Issued
Array ( [id] => 19452702 [patent_doc_number] => 20240312832 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => REDUCING PARASITIC CAPACITANCE IN FIELD-EFFECT TRANSISTORS [patent_app_type] => utility [patent_app_number] => 18/674249 [patent_app_country] => US [patent_app_date] => 2024-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7787 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18674249 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/674249
Reducing parasitic capacitance in field-effect transistors May 23, 2024 Issued
Array ( [id] => 19452938 [patent_doc_number] => 20240313068 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => INTRODUCING FLUORINE TO GATE AFTER WORK FUNCTION METAL DEPOSITION [patent_app_type] => utility [patent_app_number] => 18/674589 [patent_app_country] => US [patent_app_date] => 2024-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8089 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18674589 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/674589
Introducing fluorine to gate after work function metal deposition May 23, 2024 Issued
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