Search

Dean J. Kramer

Examiner (ID: 13130)

Most Active Art Unit
3652
Art Unit(s)
3652, 3102, 3651, 2167, 3617
Total Applications
3926
Issued Applications
3102
Pending Applications
102
Abandoned Applications
733

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19321517 [patent_doc_number] => 20240243064 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => INTEGRATED CIRCUIT DEVICE [patent_app_type] => utility [patent_app_number] => 18/453546 [patent_app_country] => US [patent_app_date] => 2023-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16519 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18453546 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/453546
INTEGRATED CIRCUIT DEVICE Aug 21, 2023 Pending
Array ( [id] => 18991273 [patent_doc_number] => 20240063242 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => IMAGE SENSOR HAVING NANO-PHOTONIC LENS ARRAY AND ELECTRONIC APPARATUS INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/235627 [patent_app_country] => US [patent_app_date] => 2023-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13128 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18235627 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/235627
IMAGE SENSOR HAVING NANO-PHOTONIC LENS ARRAY AND ELECTRONIC APPARATUS INCLUDING THE SAME Aug 17, 2023 Pending
Array ( [id] => 19452974 [patent_doc_number] => 20240313104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/450656 [patent_app_country] => US [patent_app_date] => 2023-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10552 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18450656 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/450656
SEMICONDUCTOR DEVICE Aug 15, 2023 Pending
Array ( [id] => 19733788 [patent_doc_number] => 12211790 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-28 [patent_title] => Conductive rail structure for semiconductor devices [patent_app_type] => utility [patent_app_number] => 18/447664 [patent_app_country] => US [patent_app_date] => 2023-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 12683 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18447664 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/447664
Conductive rail structure for semiconductor devices Aug 9, 2023 Issued
Array ( [id] => 18812864 [patent_doc_number] => 20230387201 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => SEMICONDUCTOR ARRANGEMENT AND METHOD OF MAKING [patent_app_type] => utility [patent_app_number] => 18/231847 [patent_app_country] => US [patent_app_date] => 2023-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9483 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18231847 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/231847
Semiconductor arrangement comprising a source pad, gate pad, drain pad, backside interconnect line, and backside contact, and backside conductive line and method of making Aug 8, 2023 Issued
Array ( [id] => 19742886 [patent_doc_number] => 12219748 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-04 [patent_title] => Semiconductor device including a dielectric layer between a source/drain region and a substrate [patent_app_type] => utility [patent_app_number] => 18/366733 [patent_app_country] => US [patent_app_date] => 2023-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3481 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18366733 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/366733
Semiconductor device including a dielectric layer between a source/drain region and a substrate Aug 7, 2023 Issued
Array ( [id] => 18851099 [patent_doc_number] => 20230413503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => EIGHT-TRANSISTOR STATIC RANDOM ACCESS MEMORY, LAYOUT THEREOF, AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/231029 [patent_app_country] => US [patent_app_date] => 2023-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15170 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 328 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18231029 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/231029
Eight-transistor static random access memory, layout thereof, and method for manufacturing the same Aug 6, 2023 Issued
Array ( [id] => 18975333 [patent_doc_number] => 20240055425 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/365452 [patent_app_country] => US [patent_app_date] => 2023-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10636 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18365452 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/365452
SEMICONDUCTOR DEVICE Aug 3, 2023 Pending
Array ( [id] => 19741349 [patent_doc_number] => 12218197 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-04 [patent_title] => Gate oxide of nanostructure transistor with increased corner thickness [patent_app_type] => utility [patent_app_number] => 18/364995 [patent_app_country] => US [patent_app_date] => 2023-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 35 [patent_no_of_words] => 7868 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18364995 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/364995
Gate oxide of nanostructure transistor with increased corner thickness Aug 2, 2023 Issued
Array ( [id] => 18789573 [patent_doc_number] => 20230378266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => GATE-ALL-AROUND DEVICE [patent_app_type] => utility [patent_app_number] => 18/362778 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15474 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362778 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/362778
Gate-all-around transistor with strained channels Jul 30, 2023 Issued
Array ( [id] => 19823567 [patent_doc_number] => 20250081774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => DISPLAY SUBSTRATE, DISPLAY DEVICE, AND DISPLAY SUBSTRATE MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 18/693966 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6386 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18693966 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/693966
DISPLAY SUBSTRATE, DISPLAY DEVICE, AND DISPLAY SUBSTRATE MANUFACTURING METHOD Jul 30, 2023 Pending
Array ( [id] => 18774495 [patent_doc_number] => 20230369326 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => INTEGRATION OF SILICON CHANNEL NANOSTRUCTURES AND SILICON-GERMANIUM CHANNEL NANOSTRUCTURES [patent_app_type] => utility [patent_app_number] => 18/360889 [patent_app_country] => US [patent_app_date] => 2023-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17393 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18360889 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/360889
Integration of silicon channel nanostructures and silicon-germanium channel nanostructures Jul 27, 2023 Issued
Array ( [id] => 19524112 [patent_doc_number] => 12125852 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-22 [patent_title] => Multi-gate transistors with backside power rail and reduced gate-drain capacitance [patent_app_type] => utility [patent_app_number] => 18/360895 [patent_app_country] => US [patent_app_date] => 2023-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 42 [patent_no_of_words] => 8983 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18360895 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/360895
Multi-gate transistors with backside power rail and reduced gate-drain capacitance Jul 27, 2023 Issued
Array ( [id] => 18774493 [patent_doc_number] => 20230369324 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => Self-Aligned Etch in Semiconductor Devices [patent_app_type] => utility [patent_app_number] => 18/358140 [patent_app_country] => US [patent_app_date] => 2023-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17191 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18358140 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/358140
Self-aligned etch in semiconductor devices Jul 24, 2023 Issued
Array ( [id] => 20260637 [patent_doc_number] => 12433008 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => FinFET structure with airgap and method of forming the same [patent_app_type] => utility [patent_app_number] => 18/358668 [patent_app_country] => US [patent_app_date] => 2023-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 62 [patent_no_of_words] => 3414 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18358668 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/358668
FinFET structure with airgap and method of forming the same Jul 24, 2023 Issued
Array ( [id] => 18774588 [patent_doc_number] => 20230369419 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => BACKSIDE CONTACT WITH AIR SPACER [patent_app_type] => utility [patent_app_number] => 18/357637 [patent_app_country] => US [patent_app_date] => 2023-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4569 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18357637 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/357637
Backside contact with air spacer Jul 23, 2023 Issued
Array ( [id] => 18757654 [patent_doc_number] => 20230361117 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => BACKSIDE PN JUNCTION DIODE [patent_app_type] => utility [patent_app_number] => 18/356802 [patent_app_country] => US [patent_app_date] => 2023-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8858 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18356802 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/356802
Backside PN junction diode Jul 20, 2023 Issued
Array ( [id] => 18757590 [patent_doc_number] => 20230361053 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => MICROELECTRONIC DEVICES WITH A POLYSILICON STRUCTURE ABOVE A STAIRCASE STRUCTURE, AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 18/356997 [patent_app_country] => US [patent_app_date] => 2023-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9669 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18356997 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/356997
Microelectronic devices with a polysilicon structure above a staircase structure, and related methods Jul 20, 2023 Issued
Array ( [id] => 19639715 [patent_doc_number] => 12170332 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-17 [patent_title] => Fin field effect transistor devices including NMOS device and PMOS device with varied geometry of work function layers [patent_app_type] => utility [patent_app_number] => 18/356256 [patent_app_country] => US [patent_app_date] => 2023-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 7785 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18356256 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/356256
Fin field effect transistor devices including NMOS device and PMOS device with varied geometry of work function layers Jul 20, 2023 Issued
Array ( [id] => 18774294 [patent_doc_number] => 20230369125 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/224088 [patent_app_country] => US [patent_app_date] => 2023-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10508 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18224088 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/224088
FinFET device structure having dielectric features between a plurality of gate electrodes and methods of forming the same Jul 19, 2023 Issued
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