
Dean Phan
Examiner (ID: 8359, Phone: (571)270-1002 , Office: P/2184 )
| Most Active Art Unit | 2184 |
| Art Unit(s) | 2184, 2182 |
| Total Applications | 611 |
| Issued Applications | 415 |
| Pending Applications | 52 |
| Abandoned Applications | 152 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
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[patent_title] => Semiconductor device and semiconductor system
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Array
(
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[patent_title] => Method and apparatus for providing C-PHY interface via FPGA IO interface
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Array
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[patent_title] => MULTI-PROCESSOR, MULTI-DOMAIN, MULTI-PROTOCOL, CACHE COHERENT, SPECULATION AWARE SHARED MEMORY AND INTERCONNECT
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Array
(
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[patent_kind] => A1
[patent_issue_date] => 2022-10-13
[patent_title] => NETWORK DEVICE CONFIGURATION BASED ON SLAVE DEVICE TYPE
[patent_app_type] => utility
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Array
(
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[patent_title] => INTEGRATED CIRCUIT, DATA PROCESSING DEVICE AND METHOD
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Array
(
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Array
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Array
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Array
(
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Array
(
[id] => 18599095
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[patent_title] => METHODS AND SYSTEMS FOR SERIAL CONTROL WITH INTERLEAVED REGISTER MAPPING
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[rel_patent_id] =>[rel_patent_doc_number] =>) 17/682452 | Methods and systems for serial control with interleaved register mapping | Feb 27, 2022 | Issued |
Array
(
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[patent_title] => METHODS FOR IDENTIFYING TARGET SLAVE ADDRESS FOR SERIAL COMMUNICATION INTERFACE
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Array
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Array
(
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Array
(
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Array
(
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Array
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Array
(
[id] => 19451198
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Array
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Array
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