
Deborah Yee
Examiner (ID: 8646, Phone: (571)272-1253 , Office: P/1734 )
| Most Active Art Unit | 1742 |
| Art Unit(s) | 1101, 1793, 1733, 1308, 1742, 1724, 3629, 1754, 1734, 1311, 2899 |
| Total Applications | 3735 |
| Issued Applications | 2973 |
| Pending Applications | 107 |
| Abandoned Applications | 657 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3942292
[patent_doc_number] => 05946579
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-31
[patent_title] => 'Stacked mask integration technique for advanced CMOS transistor formation'
[patent_app_type] => 1
[patent_app_number] => 8/987277
[patent_app_country] => US
[patent_app_date] => 1997-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 35
[patent_no_of_words] => 8485
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/946/05946579.pdf
[firstpage_image] =>[orig_patent_app_number] => 987277
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/987277 | Stacked mask integration technique for advanced CMOS transistor formation | Dec 8, 1997 | Issued |
Array
(
[id] => 4294450
[patent_doc_number] => 06184120
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-06
[patent_title] => 'Method of forming a buried plug and an interconnection'
[patent_app_type] => 1
[patent_app_number] => 8/980287
[patent_app_country] => US
[patent_app_date] => 1997-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[patent_no_of_words] => 3031
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[pdf_file] => patents/06/184/06184120.pdf
[firstpage_image] =>[orig_patent_app_number] => 980287
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/980287 | Method of forming a buried plug and an interconnection | Nov 27, 1997 | Issued |
Array
(
[id] => 3945211
[patent_doc_number] => 05953602
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-14
[patent_title] => 'EEPROM cell and related method of making thereof'
[patent_app_type] => 1
[patent_app_number] => 8/978028
[patent_app_country] => US
[patent_app_date] => 1997-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 3544
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[pdf_file] => patents/05/953/05953602.pdf
[firstpage_image] =>[orig_patent_app_number] => 978028
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/978028 | EEPROM cell and related method of making thereof | Nov 24, 1997 | Issued |
Array
(
[id] => 3945182
[patent_doc_number] => 05953600
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-14
[patent_title] => 'Fabrication of bipolar/CMOS integrated circuits'
[patent_app_type] => 1
[patent_app_number] => 8/968598
[patent_app_country] => US
[patent_app_date] => 1997-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[patent_no_of_words] => 7139
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[pdf_file] => patents/05/953/05953600.pdf
[firstpage_image] =>[orig_patent_app_number] => 968598
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/968598 | Fabrication of bipolar/CMOS integrated circuits | Nov 12, 1997 | Issued |
Array
(
[id] => 4106529
[patent_doc_number] => 06022772
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-08
[patent_title] => 'Stacked capacitor having a corrugated electrode'
[patent_app_type] => 1
[patent_app_number] => 8/966543
[patent_app_country] => US
[patent_app_date] => 1997-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
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[patent_no_of_words] => 9838
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[pdf_file] => patents/06/022/06022772.pdf
[firstpage_image] =>[orig_patent_app_number] => 966543
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/966543 | Stacked capacitor having a corrugated electrode | Nov 9, 1997 | Issued |
Array
(
[id] => 4004531
[patent_doc_number] => 05960307
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-28
[patent_title] => 'Method of forming ball grid array contacts'
[patent_app_type] => 1
[patent_app_number] => 8/964727
[patent_app_country] => US
[patent_app_date] => 1997-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[pdf_file] => patents/05/960/05960307.pdf
[firstpage_image] =>[orig_patent_app_number] => 964727
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/964727 | Method of forming ball grid array contacts | Nov 4, 1997 | Issued |
Array
(
[id] => 3964642
[patent_doc_number] => 05885859
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-23
[patent_title] => 'Methods of fabricating multi-gate, offset source and drain field effect transistors'
[patent_app_type] => 1
[patent_app_number] => 8/960631
[patent_app_country] => US
[patent_app_date] => 1997-10-29
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[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 3105
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/885/05885859.pdf
[firstpage_image] =>[orig_patent_app_number] => 960631
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/960631 | Methods of fabricating multi-gate, offset source and drain field effect transistors | Oct 28, 1997 | Issued |
Array
(
[id] => 4236773
[patent_doc_number] => 06090650
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-18
[patent_title] => 'Method to reduce timing skews in I/O circuits and clock drivers caused by fabrication process tolerances'
[patent_app_type] => 1
[patent_app_number] => 8/940303
[patent_app_country] => US
[patent_app_date] => 1997-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[pdf_file] => patents/06/090/06090650.pdf
[firstpage_image] =>[orig_patent_app_number] => 940303
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/940303 | Method to reduce timing skews in I/O circuits and clock drivers caused by fabrication process tolerances | Sep 29, 1997 | Issued |
Array
(
[id] => 4212207
[patent_doc_number] => 06028329
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-22
[patent_title] => 'Bipolar junction transistor device and a method of fabricating the same'
[patent_app_type] => 1
[patent_app_number] => 8/925357
[patent_app_country] => US
[patent_app_date] => 1997-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[pdf_file] => patents/06/028/06028329.pdf
[firstpage_image] =>[orig_patent_app_number] => 925357
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/925357 | Bipolar junction transistor device and a method of fabricating the same | Sep 7, 1997 | Issued |
Array
(
[id] => 1478169
[patent_doc_number] => 06451686
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-17
[patent_title] => 'Control of semiconductor device isolation properties through incorporation of fluorine in peteos films'
[patent_app_type] => B1
[patent_app_number] => 08/923501
[patent_app_country] => US
[patent_app_date] => 1997-09-04
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/451/06451686.pdf
[firstpage_image] =>[orig_patent_app_number] => 08923501
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/923501 | Control of semiconductor device isolation properties through incorporation of fluorine in peteos films | Sep 3, 1997 | Issued |
Array
(
[id] => 4257822
[patent_doc_number] => 06204093
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-20
[patent_title] => 'Method and apparatus for applying viscous materials to a lead frame'
[patent_app_type] => 1
[patent_app_number] => 8/916931
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[patent_app_date] => 1997-08-21
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[pdf_file] => patents/06/204/06204093.pdf
[firstpage_image] =>[orig_patent_app_number] => 916931
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/916931 | Method and apparatus for applying viscous materials to a lead frame | Aug 20, 1997 | Issued |
Array
(
[id] => 3999649
[patent_doc_number] => 05950098
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[patent_kind] => NA
[patent_issue_date] => 1999-09-07
[patent_title] => 'Manufacturing method of a semiconductor device with a silicide layer'
[patent_app_type] => 1
[patent_app_number] => 8/911979
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[firstpage_image] =>[orig_patent_app_number] => 911979
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/911979 | Manufacturing method of a semiconductor device with a silicide layer | Aug 14, 1997 | Issued |
Array
(
[id] => 3943957
[patent_doc_number] => 05998246
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-07
[patent_title] => 'Self-aligned manufacturing method of a thin film transistor for forming a single-crystal bottom-gate and an offset drain'
[patent_app_type] => 1
[patent_app_number] => 8/908721
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[pdf_file] => patents/05/998/05998246.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/908721 | Self-aligned manufacturing method of a thin film transistor for forming a single-crystal bottom-gate and an offset drain | Aug 7, 1997 | Issued |
Array
(
[id] => 4006521
[patent_doc_number] => 05888853
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[patent_issue_date] => 1999-03-30
[patent_title] => 'Integrated circuit including a graded grain structure for enhanced transistor formation and fabrication method thereof'
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[patent_app_number] => 8/905482
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[firstpage_image] =>[orig_patent_app_number] => 905482
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/905482 | Integrated circuit including a graded grain structure for enhanced transistor formation and fabrication method thereof | Jul 31, 1997 | Issued |
Array
(
[id] => 3937202
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[patent_kind] => NA
[patent_issue_date] => 1999-11-09
[patent_title] => 'SRAM cell employing substantially vertically elongated pull-up resistors and methods of making, and resistor constructions and methods of making'
[patent_app_type] => 1
[patent_app_number] => 8/902004
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[firstpage_image] =>[orig_patent_app_number] => 902004
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/902004 | SRAM cell employing substantially vertically elongated pull-up resistors and methods of making, and resistor constructions and methods of making | Jul 28, 1997 | Issued |
Array
(
[id] => 3994021
[patent_doc_number] => 05985739
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-16
[patent_title] => 'Semiconductor structures having advantageous high-frequency characteristics and processes for producing such semiconductor structures'
[patent_app_type] => 1
[patent_app_number] => 8/809222
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[firstpage_image] =>[orig_patent_app_number] => 809222
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/809222 | Semiconductor structures having advantageous high-frequency characteristics and processes for producing such semiconductor structures | Jul 28, 1997 | Issued |
Array
(
[id] => 3896632
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[patent_issue_date] => 1999-04-27
[patent_title] => 'Process of fabricating semiconductor device having low-resistive titanium silicide layer free from short-circuit and leakage current'
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[patent_app_number] => 8/883333
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Array
(
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Array
(
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Array
(
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[patent_title] => 'Method for manufacturing liquid crystal display apparatus with drain/source silicide electrodes made by sputtering process'
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[firstpage_image] =>[orig_patent_app_number] => 880505
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/880505 | Method for manufacturing liquid crystal display apparatus with drain/source silicide electrodes made by sputtering process | Jun 22, 1997 | Issued |