Search

Deborah Yee

Examiner (ID: 8646, Phone: (571)272-1253 , Office: P/1734 )

Most Active Art Unit
1742
Art Unit(s)
1101, 1793, 1733, 1308, 1742, 1724, 3629, 1754, 1734, 1311, 2899
Total Applications
3735
Issued Applications
2973
Pending Applications
107
Abandoned Applications
657

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4050259 [patent_doc_number] => 05943559 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Method for manufacturing liquid crystal display apparatus with drain/source silicide electrodes made by sputtering process' [patent_app_type] => 1 [patent_app_number] => 8/880505 [patent_app_country] => US [patent_app_date] => 1997-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 27 [patent_no_of_words] => 4761 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/943/05943559.pdf [firstpage_image] =>[orig_patent_app_number] => 880505 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/880505
Method for manufacturing liquid crystal display apparatus with drain/source silicide electrodes made by sputtering process Jun 22, 1997 Issued
Array ( [id] => 4245737 [patent_doc_number] => 06136647 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Method of forming interpoly dielectric and gate oxide in a memory cell' [patent_app_type] => 1 [patent_app_number] => 8/856057 [patent_app_country] => US [patent_app_date] => 1997-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 4264 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/136/06136647.pdf [firstpage_image] =>[orig_patent_app_number] => 856057 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/856057
Method of forming interpoly dielectric and gate oxide in a memory cell May 13, 1997 Issued
Array ( [id] => 4353511 [patent_doc_number] => 06218228 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'DMOS device structure, and related manufacturing process' [patent_app_type] => 1 [patent_app_number] => 8/856261 [patent_app_country] => US [patent_app_date] => 1997-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2796 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218228.pdf [firstpage_image] =>[orig_patent_app_number] => 856261 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/856261
DMOS device structure, and related manufacturing process May 13, 1997 Issued
Array ( [id] => 4016620 [patent_doc_number] => 05923995 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Methods and apparatuses for singulation of microelectromechanical systems' [patent_app_type] => 1 [patent_app_number] => 8/844467 [patent_app_country] => US [patent_app_date] => 1997-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 3867 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/923/05923995.pdf [firstpage_image] =>[orig_patent_app_number] => 844467 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/844467
Methods and apparatuses for singulation of microelectromechanical systems Apr 17, 1997 Issued
Array ( [id] => 3941967 [patent_doc_number] => 05946557 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Method of manufacturing a semiconductor device having dummy patterns and an upper insulating layer having cavities' [patent_app_type] => 1 [patent_app_number] => 8/834041 [patent_app_country] => US [patent_app_date] => 1997-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 3633 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/946/05946557.pdf [firstpage_image] =>[orig_patent_app_number] => 834041 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/834041
Method of manufacturing a semiconductor device having dummy patterns and an upper insulating layer having cavities Apr 10, 1997 Issued
Array ( [id] => 3968800 [patent_doc_number] => 05904516 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-18 [patent_title] => 'Transistor structure and method for fabricating the same' [patent_app_type] => 1 [patent_app_number] => 8/838607 [patent_app_country] => US [patent_app_date] => 1997-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 1565 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/904/05904516.pdf [firstpage_image] =>[orig_patent_app_number] => 838607 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/838607
Transistor structure and method for fabricating the same Apr 8, 1997 Issued
Array ( [id] => 3996112 [patent_doc_number] => 05922621 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Quantum semiconductor device and a fabrication process thereof' [patent_app_type] => 1 [patent_app_number] => 8/832185 [patent_app_country] => US [patent_app_date] => 1997-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 6149 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/922/05922621.pdf [firstpage_image] =>[orig_patent_app_number] => 832185 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/832185
Quantum semiconductor device and a fabrication process thereof Apr 7, 1997 Issued
Array ( [id] => 3944378 [patent_doc_number] => 05976989 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Thin film transistor fabrication method, active matrix substrate fabrication method, and liquid crystal display device' [patent_app_type] => 1 [patent_app_number] => 8/809935 [patent_app_country] => US [patent_app_date] => 1997-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 36 [patent_no_of_words] => 12191 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/976/05976989.pdf [firstpage_image] =>[orig_patent_app_number] => 809935 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/809935
Thin film transistor fabrication method, active matrix substrate fabrication method, and liquid crystal display device Apr 2, 1997 Issued
Array ( [id] => 4069782 [patent_doc_number] => 05933731 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Semiconductor device having gate oxide films having different thicknesses and manufacturing method thereof' [patent_app_type] => 1 [patent_app_number] => 8/823979 [patent_app_country] => US [patent_app_date] => 1997-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 24 [patent_no_of_words] => 3737 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/933/05933731.pdf [firstpage_image] =>[orig_patent_app_number] => 823979 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/823979
Semiconductor device having gate oxide films having different thicknesses and manufacturing method thereof Mar 24, 1997 Issued
Array ( [id] => 3942268 [patent_doc_number] => 05990009 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Maximization of low dielectric constant material between interconnect traces of a semiconductor circuit' [patent_app_type] => 1 [patent_app_number] => 8/805607 [patent_app_country] => US [patent_app_date] => 1997-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 2960 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/990/05990009.pdf [firstpage_image] =>[orig_patent_app_number] => 805607 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/805607
Maximization of low dielectric constant material between interconnect traces of a semiconductor circuit Feb 24, 1997 Issued
08/803693 SEMICONDUCTOR THIN FILM AND ITS MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD Feb 23, 1997 Abandoned
Array ( [id] => 3944486 [patent_doc_number] => 05998284 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/803753 [patent_app_country] => US [patent_app_date] => 1997-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 25 [patent_no_of_words] => 7284 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/998/05998284.pdf [firstpage_image] =>[orig_patent_app_number] => 803753 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/803753
Method for manufacturing semiconductor device Feb 20, 1997 Issued
Array ( [id] => 4039306 [patent_doc_number] => 05926735 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Method of forming semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/802685 [patent_app_country] => US [patent_app_date] => 1997-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 49 [patent_no_of_words] => 10479 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926735.pdf [firstpage_image] =>[orig_patent_app_number] => 802685 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/802685
Method of forming semiconductor device Feb 18, 1997 Issued
Array ( [id] => 4141967 [patent_doc_number] => 06030888 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Method of fabricating high-voltage junction-isolated semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 8/792483 [patent_app_country] => US [patent_app_date] => 1997-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 2593 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/030/06030888.pdf [firstpage_image] =>[orig_patent_app_number] => 792483 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/792483
Method of fabricating high-voltage junction-isolated semiconductor devices Jan 30, 1997 Issued
Array ( [id] => 4050318 [patent_doc_number] => 05943563 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Method for producing a three-dimensional circuit arrangement' [patent_app_type] => 1 [patent_app_number] => 8/776557 [patent_app_country] => US [patent_app_date] => 1997-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2530 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/943/05943563.pdf [firstpage_image] =>[orig_patent_app_number] => 776557 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/776557
Method for producing a three-dimensional circuit arrangement Jan 29, 1997 Issued
Array ( [id] => 3942382 [patent_doc_number] => 05946585 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Method of fabricating semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/789089 [patent_app_country] => US [patent_app_date] => 1997-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 6198 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/946/05946585.pdf [firstpage_image] =>[orig_patent_app_number] => 789089 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/789089
Method of fabricating semiconductor device Jan 26, 1997 Issued
Array ( [id] => 4094731 [patent_doc_number] => 06096610 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Transistor suitable for high voltage circuit' [patent_app_type] => 1 [patent_app_number] => 8/780415 [patent_app_country] => US [patent_app_date] => 1997-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 8274 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/096/06096610.pdf [firstpage_image] =>[orig_patent_app_number] => 780415 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/780415
Transistor suitable for high voltage circuit Jan 7, 1997 Issued
Array ( [id] => 3917911 [patent_doc_number] => 05927991 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Method for forming triple well in semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/772289 [patent_app_country] => US [patent_app_date] => 1996-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2111 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/927/05927991.pdf [firstpage_image] =>[orig_patent_app_number] => 772289 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/772289
Method for forming triple well in semiconductor device Dec 22, 1996 Issued
Array ( [id] => 3941827 [patent_doc_number] => 05946547 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Liquid crystal display device fabrication methods with reduced numbers of patterning steps' [patent_app_type] => 1 [patent_app_number] => 8/766757 [patent_app_country] => US [patent_app_date] => 1996-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 2020 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/946/05946547.pdf [firstpage_image] =>[orig_patent_app_number] => 766757 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/766757
Liquid crystal display device fabrication methods with reduced numbers of patterning steps Dec 12, 1996 Issued
Array ( [id] => 4106397 [patent_doc_number] => 06022764 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-08 [patent_title] => 'Exposure apparatus and method for forming thin film transistor' [patent_app_type] => 1 [patent_app_number] => 8/761961 [patent_app_country] => US [patent_app_date] => 1996-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 2141 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/022/06022764.pdf [firstpage_image] =>[orig_patent_app_number] => 761961 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/761961
Exposure apparatus and method for forming thin film transistor Dec 8, 1996 Issued
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