Search

Deborah Yee

Examiner (ID: 8646, Phone: (571)272-1253 , Office: P/1734 )

Most Active Art Unit
1742
Art Unit(s)
1101, 1793, 1733, 1308, 1742, 1724, 3629, 1754, 1734, 1311, 2899
Total Applications
3735
Issued Applications
2973
Pending Applications
107
Abandoned Applications
657

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6985585 [patent_doc_number] => 20010035557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-01 [patent_title] => 'Methods for fabricating CMOS integrated circuits including a source/drain plug' [patent_app_type] => new [patent_app_number] => 09/885432 [patent_app_country] => US [patent_app_date] => 2001-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4792 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20010035557.pdf [firstpage_image] =>[orig_patent_app_number] => 09885432 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/885432
Methods for fabricating CMOS integrated circuits including source/drain compensating regions Jun 19, 2001 Issued
Array ( [id] => 1580977 [patent_doc_number] => 06423571 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Method of making a semiconductor device having a stress relieving mechanism' [patent_app_type] => B1 [patent_app_number] => 09/884378 [patent_app_country] => US [patent_app_date] => 2001-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5295 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/423/06423571.pdf [firstpage_image] =>[orig_patent_app_number] => 09884378 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/884378
Method of making a semiconductor device having a stress relieving mechanism Jun 19, 2001 Issued
Array ( [id] => 1273876 [patent_doc_number] => 06649480 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-18 [patent_title] => 'Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs' [patent_app_type] => B2 [patent_app_number] => 09/884172 [patent_app_country] => US [patent_app_date] => 2001-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 5534 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/649/06649480.pdf [firstpage_image] =>[orig_patent_app_number] => 09884172 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/884172
Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs Jun 18, 2001 Issued
Array ( [id] => 5814880 [patent_doc_number] => 20020039819 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-04 [patent_title] => 'Method for manufacturing a field effect transistor' [patent_app_type] => new [patent_app_number] => 09/883821 [patent_app_country] => US [patent_app_date] => 2001-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4093 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0039/20020039819.pdf [firstpage_image] =>[orig_patent_app_number] => 09883821 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/883821
Method for manufacturing a field effect transistor Jun 17, 2001 Abandoned
Array ( [id] => 1415375 [patent_doc_number] => 06511889 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-01-28 [patent_title] => 'Reference voltage supply circuit having reduced dispersion of an output voltage' [patent_app_type] => B2 [patent_app_number] => 09/878972 [patent_app_country] => US [patent_app_date] => 2001-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 12174 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/511/06511889.pdf [firstpage_image] =>[orig_patent_app_number] => 09878972 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/878972
Reference voltage supply circuit having reduced dispersion of an output voltage Jun 12, 2001 Issued
Array ( [id] => 1529592 [patent_doc_number] => 06479903 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-12 [patent_title] => 'Flip chip thermally enhanced ball grid array' [patent_app_type] => B2 [patent_app_number] => 09/877324 [patent_app_country] => US [patent_app_date] => 2001-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2699 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 314 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/479/06479903.pdf [firstpage_image] =>[orig_patent_app_number] => 09877324 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/877324
Flip chip thermally enhanced ball grid array Jun 10, 2001 Issued
Array ( [id] => 1284187 [patent_doc_number] => 06642542 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-04 [patent_title] => 'Large EL panel and manufacturing method therefor' [patent_app_type] => B1 [patent_app_number] => 09/856852 [patent_app_country] => US [patent_app_date] => 2001-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 3666 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/642/06642542.pdf [firstpage_image] =>[orig_patent_app_number] => 09856852 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/856852
Large EL panel and manufacturing method therefor May 28, 2001 Issued
Array ( [id] => 6111295 [patent_doc_number] => 20020173092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-21 [patent_title] => 'Forming devices on a semiconductor substrate' [patent_app_type] => new [patent_app_number] => 09/860932 [patent_app_country] => US [patent_app_date] => 2001-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 2011 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20020173092.pdf [firstpage_image] =>[orig_patent_app_number] => 09860932 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/860932
Forming devices on a semiconductor substrate May 17, 2001 Abandoned
Array ( [id] => 1393720 [patent_doc_number] => 06541322 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-01 [patent_title] => 'Method for preventing gate depletion effects of MOS transistor' [patent_app_type] => B2 [patent_app_number] => 09/858512 [patent_app_country] => US [patent_app_date] => 2001-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 1704 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/541/06541322.pdf [firstpage_image] =>[orig_patent_app_number] => 09858512 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/858512
Method for preventing gate depletion effects of MOS transistor May 16, 2001 Issued
Array ( [id] => 6109529 [patent_doc_number] => 20020172244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-21 [patent_title] => 'Self-separating laser diode assembly and method' [patent_app_type] => new [patent_app_number] => 09/861232 [patent_app_country] => US [patent_app_date] => 2001-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5659 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20020172244.pdf [firstpage_image] =>[orig_patent_app_number] => 09861232 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/861232
Self-separating laser diode assembly and method May 16, 2001 Abandoned
Array ( [id] => 6111227 [patent_doc_number] => 20020173062 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-21 [patent_title] => 'Method for manufacturing GaN-based LED' [patent_app_type] => new [patent_app_number] => 09/861402 [patent_app_country] => US [patent_app_date] => 2001-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2338 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20020173062.pdf [firstpage_image] =>[orig_patent_app_number] => 09861402 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/861402
Method for manufacturing GaN-based LED May 16, 2001 Abandoned
Array ( [id] => 1107619 [patent_doc_number] => 06808974 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-26 [patent_title] => 'CMOS structure with maximized polysilicon gate activation and a method for selectively maximizing doping activation in gate, extension, and source/drain regions' [patent_app_type] => B2 [patent_app_number] => 09/859021 [patent_app_country] => US [patent_app_date] => 2001-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 3271 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/808/06808974.pdf [firstpage_image] =>[orig_patent_app_number] => 09859021 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/859021
CMOS structure with maximized polysilicon gate activation and a method for selectively maximizing doping activation in gate, extension, and source/drain regions May 14, 2001 Issued
Array ( [id] => 7000573 [patent_doc_number] => 20010053574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-20 [patent_title] => 'Method for fabricating a semiconductor component having a wiring which runs piecewise in the substrate, and also a semiconductor component which can be fabricated by this method' [patent_app_type] => new [patent_app_number] => 09/853521 [patent_app_country] => US [patent_app_date] => 2001-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3576 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20010053574.pdf [firstpage_image] =>[orig_patent_app_number] => 09853521 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/853521
Method for fabricating a semiconductor component having a wiring which runs piecewise in the substrate, and also a semiconductor component which can be fabricated by this method May 10, 2001 Issued
Array ( [id] => 5798598 [patent_doc_number] => 20020008304 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-24 [patent_title] => 'Scanning probe microscope (SPM) probe having field effect transistor channel and method of fabricating the same' [patent_app_type] => new [patent_app_number] => 09/851411 [patent_app_country] => US [patent_app_date] => 2001-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4000 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20020008304.pdf [firstpage_image] =>[orig_patent_app_number] => 09851411 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/851411
Scanning probe microscope (SPM) probe having field effect transistor channel and method of fabricating the same May 7, 2001 Issued
Array ( [id] => 1332414 [patent_doc_number] => 06596611 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-22 [patent_title] => 'Method for forming wafer level package having serpentine-shaped electrode along scribe line and package formed' [patent_app_type] => B2 [patent_app_number] => 09/846932 [patent_app_country] => US [patent_app_date] => 2001-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 15 [patent_no_of_words] => 3674 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/596/06596611.pdf [firstpage_image] =>[orig_patent_app_number] => 09846932 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/846932
Method for forming wafer level package having serpentine-shaped electrode along scribe line and package formed Apr 30, 2001 Issued
Array ( [id] => 6175402 [patent_doc_number] => 20020155364 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-24 [patent_title] => 'Method and system to achieve thermal transfer between a workpiece and a heated body disposed in a chamber' [patent_app_type] => new [patent_app_number] => 09/838126 [patent_app_country] => US [patent_app_date] => 2001-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7067 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20020155364.pdf [firstpage_image] =>[orig_patent_app_number] => 09838126 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/838126
Method and system to achieve thermal transfer between a workpiece and a heated body disposed in a chamber Apr 19, 2001 Abandoned
Array ( [id] => 1189966 [patent_doc_number] => 06734538 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-11 [patent_title] => 'Article comprising a multi-layer electronic package and method therefor' [patent_app_type] => B1 [patent_app_number] => 09/834022 [patent_app_country] => US [patent_app_date] => 2001-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 4445 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/734/06734538.pdf [firstpage_image] =>[orig_patent_app_number] => 09834022 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/834022
Article comprising a multi-layer electronic package and method therefor Apr 11, 2001 Issued
Array ( [id] => 1416033 [patent_doc_number] => 06509206 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-01-21 [patent_title] => 'Method and apparatus for manufacturing semiconductor device, and semiconductor device manufactured by the method' [patent_app_type] => B2 [patent_app_number] => 09/828942 [patent_app_country] => US [patent_app_date] => 2001-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 20 [patent_no_of_words] => 4800 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/509/06509206.pdf [firstpage_image] =>[orig_patent_app_number] => 09828942 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/828942
Method and apparatus for manufacturing semiconductor device, and semiconductor device manufactured by the method Apr 9, 2001 Issued
Array ( [id] => 6920614 [patent_doc_number] => 20010028099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-11 [patent_title] => 'Semiconductor device and manufacturing method therefor' [patent_app_type] => new [patent_app_number] => 09/820781 [patent_app_country] => US [patent_app_date] => 2001-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 9063 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20010028099.pdf [firstpage_image] =>[orig_patent_app_number] => 09820781 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/820781
Semiconductor device and manufacturing method therefor Mar 29, 2001 Abandoned
Array ( [id] => 6886603 [patent_doc_number] => 20010019872 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-06 [patent_title] => 'Transistor and method' [patent_app_type] => new [patent_app_number] => 09/821602 [patent_app_country] => US [patent_app_date] => 2001-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2093 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20010019872.pdf [firstpage_image] =>[orig_patent_app_number] => 09821602 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/821602
Transistor and method Mar 28, 2001 Issued
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