Search

Debra Chun

Examiner (ID: 11282)

Most Active Art Unit
2308
Art Unit(s)
2308, 2307
Total Applications
364
Issued Applications
277
Pending Applications
0
Abandoned Applications
87

Applications

Application numberTitle of the applicationFiling DateStatus
08/135754 MULTI-PROCESSOR WITH CROSSBAR LINK OF PROCESSORS AND MEMORIES AND METHOD OF OPERATION Oct 11, 1993 Abandoned
Array ( [id] => 3106960 [patent_doc_number] => 05313601 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-17 [patent_title] => 'Request control apparatus' [patent_app_type] => 1 [patent_app_number] => 8/091741 [patent_app_country] => US [patent_app_date] => 1993-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 8575 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/313/05313601.pdf [firstpage_image] =>[orig_patent_app_number] => 091741 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/091741
Request control apparatus Jul 13, 1993 Issued
Array ( [id] => 3108418 [patent_doc_number] => 05293490 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-08 [patent_title] => 'Data buffering device having simple data reading and/or storing function' [patent_app_type] => 1 [patent_app_number] => 8/054821 [patent_app_country] => US [patent_app_date] => 1993-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 9439 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 624 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/293/05293490.pdf [firstpage_image] =>[orig_patent_app_number] => 054821 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/054821
Data buffering device having simple data reading and/or storing function Apr 29, 1993 Issued
Array ( [id] => 3108564 [patent_doc_number] => 05293498 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-08 [patent_title] => 'Arrangement of designation of drive element number using mother boards' [patent_app_type] => 1 [patent_app_number] => 8/049879 [patent_app_country] => US [patent_app_date] => 1993-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4113 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/293/05293498.pdf [firstpage_image] =>[orig_patent_app_number] => 049879 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/049879
Arrangement of designation of drive element number using mother boards Apr 18, 1993 Issued
Array ( [id] => 3064424 [patent_doc_number] => 05325491 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-06-28 [patent_title] => 'Method and apparatus for extending a computer bus' [patent_app_type] => 1 [patent_app_number] => 8/047018 [patent_app_country] => US [patent_app_date] => 1993-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 6298 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/325/05325491.pdf [firstpage_image] =>[orig_patent_app_number] => 047018 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/047018
Method and apparatus for extending a computer bus Apr 12, 1993 Issued
Array ( [id] => 3102646 [patent_doc_number] => 05278959 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-11 [patent_title] => 'Processor usable as a bus master or a bus slave' [patent_app_type] => 1 [patent_app_number] => 7/490172 [patent_app_country] => US [patent_app_date] => 1993-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 28 [patent_no_of_words] => 21220 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/278/05278959.pdf [firstpage_image] =>[orig_patent_app_number] => 490172 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/490172
Processor usable as a bus master or a bus slave Mar 12, 1993 Issued
Array ( [id] => 2951129 [patent_doc_number] => 05261058 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-09 [patent_title] => 'Multiple microcontroller hard disk drive control architecture' [patent_app_type] => 1 [patent_app_number] => 8/027614 [patent_app_country] => US [patent_app_date] => 1993-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 16122 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/261/05261058.pdf [firstpage_image] =>[orig_patent_app_number] => 027614 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/027614
Multiple microcontroller hard disk drive control architecture Mar 4, 1993 Issued
08/015874 MULTIPLE INPUT BUFFERS FOR ADDRESS BITS Feb 2, 1993 Abandoned
Array ( [id] => 3035170 [patent_doc_number] => 05327540 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-05 [patent_title] => 'Method and apparatus for decoding bus master arbitration levels to optimize memory transfers' [patent_app_type] => 1 [patent_app_number] => 8/016652 [patent_app_country] => US [patent_app_date] => 1993-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2626 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/327/05327540.pdf [firstpage_image] =>[orig_patent_app_number] => 016652 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/016652
Method and apparatus for decoding bus master arbitration levels to optimize memory transfers Jan 31, 1993 Issued
Array ( [id] => 3071317 [patent_doc_number] => 05339448 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-16 [patent_title] => 'Microprocessor with improved internal transmission' [patent_app_type] => 1 [patent_app_number] => 8/015296 [patent_app_country] => US [patent_app_date] => 1993-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 6224 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/339/05339448.pdf [firstpage_image] =>[orig_patent_app_number] => 015296 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/015296
Microprocessor with improved internal transmission Jan 21, 1993 Issued
Array ( [id] => 3063271 [patent_doc_number] => 05305443 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-19 [patent_title] => 'Microprocessor with low power bus' [patent_app_type] => 1 [patent_app_number] => 8/008053 [patent_app_country] => US [patent_app_date] => 1993-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2237 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/305/05305443.pdf [firstpage_image] =>[orig_patent_app_number] => 008053 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/008053
Microprocessor with low power bus Jan 21, 1993 Issued
Array ( [id] => 2976639 [patent_doc_number] => 05274773 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-28 [patent_title] => 'Flexible host interface controller architecture' [patent_app_type] => 1 [patent_app_number] => 7/997860 [patent_app_country] => US [patent_app_date] => 1992-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 16147 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/274/05274773.pdf [firstpage_image] =>[orig_patent_app_number] => 997860 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/997860
Flexible host interface controller architecture Dec 28, 1992 Issued
Array ( [id] => 3049522 [patent_doc_number] => 05301275 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-05 [patent_title] => 'Data transfer system with variable data buffer size and programmable interrupt frequency' [patent_app_type] => 1 [patent_app_number] => 7/996524 [patent_app_country] => US [patent_app_date] => 1992-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 28294 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/301/05301275.pdf [firstpage_image] =>[orig_patent_app_number] => 996524 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/996524
Data transfer system with variable data buffer size and programmable interrupt frequency Dec 22, 1992 Issued
Array ( [id] => 3050656 [patent_doc_number] => 05301332 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-05 [patent_title] => 'Method and apparatus for a dynamic, timed-loop arbitration' [patent_app_type] => 1 [patent_app_number] => 7/995731 [patent_app_country] => US [patent_app_date] => 1992-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4135 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/301/05301332.pdf [firstpage_image] =>[orig_patent_app_number] => 995731 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/995731
Method and apparatus for a dynamic, timed-loop arbitration Dec 22, 1992 Issued
Array ( [id] => 3071224 [patent_doc_number] => 05339443 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-16 [patent_title] => 'Arbitrating multiprocessor accesses to shared resources' [patent_app_type] => 1 [patent_app_number] => 7/991497 [patent_app_country] => US [patent_app_date] => 1992-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4374 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 326 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/339/05339443.pdf [firstpage_image] =>[orig_patent_app_number] => 991497 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/991497
Arbitrating multiprocessor accesses to shared resources Dec 16, 1992 Issued
Array ( [id] => 3064622 [patent_doc_number] => 05307463 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-26 [patent_title] => 'Programmable controller communication module' [patent_app_type] => 1 [patent_app_number] => 7/987104 [patent_app_country] => US [patent_app_date] => 1992-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7182 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/307/05307463.pdf [firstpage_image] =>[orig_patent_app_number] => 987104 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/987104
Programmable controller communication module Dec 6, 1992 Issued
Array ( [id] => 3063222 [patent_doc_number] => 05283899 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-02-01 [patent_title] => 'First-in/first-out buffer queue management for multiple processes' [patent_app_type] => 1 [patent_app_number] => 7/982251 [patent_app_country] => US [patent_app_date] => 1992-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4001 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/283/05283899.pdf [firstpage_image] =>[orig_patent_app_number] => 982251 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/982251
First-in/first-out buffer queue management for multiple processes Nov 24, 1992 Issued
Array ( [id] => 3058811 [patent_doc_number] => 05287484 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-02-15 [patent_title] => 'Multi-processor system for invalidating hierarchical cache' [patent_app_type] => 1 [patent_app_number] => 7/976645 [patent_app_country] => US [patent_app_date] => 1992-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8909 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 578 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/287/05287484.pdf [firstpage_image] =>[orig_patent_app_number] => 976645 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/976645
Multi-processor system for invalidating hierarchical cache Nov 12, 1992 Issued
Array ( [id] => 3033110 [patent_doc_number] => 05303382 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-12 [patent_title] => 'Arbiter with programmable dynamic request prioritization' [patent_app_type] => 1 [patent_app_number] => 7/975127 [patent_app_country] => US [patent_app_date] => 1992-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4938 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 327 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/303/05303382.pdf [firstpage_image] =>[orig_patent_app_number] => 975127 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/975127
Arbiter with programmable dynamic request prioritization Nov 11, 1992 Issued
Array ( [id] => 3053157 [patent_doc_number] => 05377334 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-27 [patent_title] => 'Fast asynchronous resource master-slave combination' [patent_app_type] => 1 [patent_app_number] => 7/974375 [patent_app_country] => US [patent_app_date] => 1992-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 5562 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 388 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/377/05377334.pdf [firstpage_image] =>[orig_patent_app_number] => 974375 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/974375
Fast asynchronous resource master-slave combination Nov 9, 1992 Issued
Menu