Search

Debra Chun

Examiner (ID: 8356)

Most Active Art Unit
2308
Art Unit(s)
2307, 2308
Total Applications
364
Issued Applications
277
Pending Applications
0
Abandoned Applications
87

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2752218 [patent_doc_number] => 05029069 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-07-02 [patent_title] => 'Data processor' [patent_app_type] => 1 [patent_app_number] => 7/171581 [patent_app_country] => US [patent_app_date] => 1988-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 214 [patent_figures_cnt] => 399 [patent_no_of_words] => 93718 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/029/05029069.pdf [firstpage_image] =>[orig_patent_app_number] => 171581 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/171581
Data processor Mar 21, 1988 Issued
Array ( [id] => 2633423 [patent_doc_number] => 04920480 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-04-24 [patent_title] => 'Digital signal processor' [patent_app_type] => 1 [patent_app_number] => 7/164257 [patent_app_country] => US [patent_app_date] => 1988-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4603 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/920/04920480.pdf [firstpage_image] =>[orig_patent_app_number] => 164257 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/164257
Digital signal processor Mar 3, 1988 Issued
Array ( [id] => 2636344 [patent_doc_number] => 04951248 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-08-21 [patent_title] => 'Self configuring memory system' [patent_app_type] => 1 [patent_app_number] => 7/164092 [patent_app_country] => US [patent_app_date] => 1988-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3135 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 353 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/951/04951248.pdf [firstpage_image] =>[orig_patent_app_number] => 164092 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/164092
Self configuring memory system Mar 3, 1988 Issued
Array ( [id] => 2639850 [patent_doc_number] => 04977495 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-12-11 [patent_title] => 'System and method for accessing a cache memory which is located in the main memory of a large data processing system' [patent_app_type] => 1 [patent_app_number] => 7/162396 [patent_app_country] => US [patent_app_date] => 1988-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3200 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/977/04977495.pdf [firstpage_image] =>[orig_patent_app_number] => 162396 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/162396
System and method for accessing a cache memory which is located in the main memory of a large data processing system Feb 28, 1988 Issued
07/158430 DATA TRANSFER CONTROL UNIT Feb 21, 1988 Abandoned
07/158406 PROCEDURE FOR THE CONFIGURATION OF A BUS-TYPE DATA TRANSMISSION NETWORK Feb 21, 1988 Abandoned
Array ( [id] => 2961744 [patent_doc_number] => 05222232 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-06-22 [patent_title] => 'Apparatus and method for monitoring PROM access in a microcomputer' [patent_app_type] => 1 [patent_app_number] => 7/146986 [patent_app_country] => US [patent_app_date] => 1988-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1074 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/222/05222232.pdf [firstpage_image] =>[orig_patent_app_number] => 146986 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/146986
Apparatus and method for monitoring PROM access in a microcomputer Jan 21, 1988 Issued
07/146001 INTEGRATED CACHE UNIT Jan 19, 1988 Abandoned
07/140055 PASSIVE PROCESSOR COMMUNICATIONS INTERFACE Dec 30, 1987 Abandoned
Array ( [id] => 2635536 [patent_doc_number] => 04967338 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-10-30 [patent_title] => 'Loosely coupled pipeline processor' [patent_app_type] => 1 [patent_app_number] => 7/137923 [patent_app_country] => US [patent_app_date] => 1987-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6690 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/967/04967338.pdf [firstpage_image] =>[orig_patent_app_number] => 137923 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/137923
Loosely coupled pipeline processor Dec 27, 1987 Issued
Array ( [id] => 2707108 [patent_doc_number] => 04989113 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-01-29 [patent_title] => 'Data processing device having direct memory access with improved transfer control' [patent_app_type] => 1 [patent_app_number] => 7/138419 [patent_app_country] => US [patent_app_date] => 1987-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 18989 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/989/04989113.pdf [firstpage_image] =>[orig_patent_app_number] => 138419 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/138419
Data processing device having direct memory access with improved transfer control Dec 27, 1987 Issued
Array ( [id] => 2564455 [patent_doc_number] => 04961135 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-10-02 [patent_title] => 'Translation lookaside buffer control system' [patent_app_type] => 1 [patent_app_number] => 7/137082 [patent_app_country] => US [patent_app_date] => 1987-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 7275 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/961/04961135.pdf [firstpage_image] =>[orig_patent_app_number] => 137082 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/137082
Translation lookaside buffer control system Dec 22, 1987 Issued
Array ( [id] => 2867561 [patent_doc_number] => 05113510 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-05-12 [patent_title] => 'Method and apparatus for operating a cache memory in a multi-processor' [patent_app_type] => 1 [patent_app_number] => 7/136580 [patent_app_country] => US [patent_app_date] => 1987-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6220 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/113/05113510.pdf [firstpage_image] =>[orig_patent_app_number] => 136580 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/136580
Method and apparatus for operating a cache memory in a multi-processor Dec 21, 1987 Issued
07/136138 MEMORY MANAGEMENT DEVICE Dec 20, 1987 Abandoned
Array ( [id] => 2639318 [patent_doc_number] => 04916658 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-04-10 [patent_title] => 'Dynamic buffer control' [patent_app_type] => 1 [patent_app_number] => 7/135170 [patent_app_country] => US [patent_app_date] => 1987-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3217 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/916/04916658.pdf [firstpage_image] =>[orig_patent_app_number] => 135170 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/135170
Dynamic buffer control Dec 17, 1987 Issued
Array ( [id] => 2613165 [patent_doc_number] => 04932040 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-06-05 [patent_title] => 'Bidirectional control signalling bus interface apparatus for transmitting signals between two bus systems' [patent_app_type] => 1 [patent_app_number] => 7/129278 [patent_app_country] => US [patent_app_date] => 1987-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4246 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/932/04932040.pdf [firstpage_image] =>[orig_patent_app_number] => 129278 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/129278
Bidirectional control signalling bus interface apparatus for transmitting signals between two bus systems Dec 6, 1987 Issued
Array ( [id] => 2742211 [patent_doc_number] => 05040141 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-08-13 [patent_title] => 'Method for administrating reply mail in electronic mail system' [patent_app_type] => 1 [patent_app_number] => 7/123930 [patent_app_country] => US [patent_app_date] => 1987-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 2933 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/040/05040141.pdf [firstpage_image] =>[orig_patent_app_number] => 123930 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/123930
Method for administrating reply mail in electronic mail system Nov 22, 1987 Issued
07/122292 METHOD AND APPARATUS FOR CONTROLLING FLOW IN A DATA BUS Nov 17, 1987 Abandoned
07/119758 DIRECT CONTROL FACILITY FOR MULTIPROCESSOR NETWORK Nov 11, 1987 Abandoned
Array ( [id] => 2676843 [patent_doc_number] => 04905144 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-02-27 [patent_title] => 'High speed path optimization co-processor' [patent_app_type] => 1 [patent_app_number] => 7/116804 [patent_app_country] => US [patent_app_date] => 1987-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 19 [patent_no_of_words] => 4443 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 385 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/905/04905144.pdf [firstpage_image] =>[orig_patent_app_number] => 116804 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/116804
High speed path optimization co-processor Nov 1, 1987 Issued
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