| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 3035712
[patent_doc_number] => 05289587
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-02-22
[patent_title] => 'Apparatus for and method of providing the program counter of a microprocessor external to the device'
[patent_app_type] => 1
[patent_app_number] => 7/973208
[patent_app_country] => US
[patent_app_date] => 1992-11-06
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[pdf_file] => patents/05/289/05289587.pdf
[firstpage_image] =>[orig_patent_app_number] => 973208
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/973208 | Apparatus for and method of providing the program counter of a microprocessor external to the device | Nov 5, 1992 | Issued |
Array
(
[id] => 3064604
[patent_doc_number] => 05307462
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-04-26
[patent_title] => 'Switch for sharing a peripheral device'
[patent_app_type] => 1
[patent_app_number] => 7/964573
[patent_app_country] => US
[patent_app_date] => 1992-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 3208
[patent_no_of_claims] => 22
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[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/307/05307462.pdf
[firstpage_image] =>[orig_patent_app_number] => 964573
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/964573 | Switch for sharing a peripheral device | Oct 20, 1992 | Issued |
Array
(
[id] => 3087087
[patent_doc_number] => 05323403
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-06-21
[patent_title] => 'Method and apparatus for maximizing process throughput'
[patent_app_type] => 1
[patent_app_number] => 7/960171
[patent_app_country] => US
[patent_app_date] => 1992-10-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 4375
[patent_no_of_claims] => 17
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[patent_words_short_claim] => 132
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/323/05323403.pdf
[firstpage_image] =>[orig_patent_app_number] => 960171
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/960171 | Method and apparatus for maximizing process throughput | Oct 12, 1992 | Issued |
Array
(
[id] => 2908575
[patent_doc_number] => 05241680
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-08-31
[patent_title] => 'Low-power, standby mode computer'
[patent_app_type] => 1
[patent_app_number] => 7/958983
[patent_app_country] => US
[patent_app_date] => 1992-10-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 17
[patent_no_of_words] => 8601
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 227
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/241/05241680.pdf
[firstpage_image] =>[orig_patent_app_number] => 958983
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/958983 | Low-power, standby mode computer | Oct 8, 1992 | Issued |
Array
(
[id] => 3062943
[patent_doc_number] => 05283886
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-02-01
[patent_title] => 'Multiprocessor cache system having three states for generating invalidating signals upon write accesses'
[patent_app_type] => 1
[patent_app_number] => 7/950746
[patent_app_country] => US
[patent_app_date] => 1992-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_words] => 18766
[patent_no_of_claims] => 14
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[patent_words_short_claim] => 647
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/283/05283886.pdf
[firstpage_image] =>[orig_patent_app_number] => 950746
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/950746 | Multiprocessor cache system having three states for generating invalidating signals upon write accesses | Sep 23, 1992 | Issued |
Array
(
[id] => 3035694
[patent_doc_number] => 05289586
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-02-22
[patent_title] => 'Digital information transmission apparatus and method of driving information transmission bus system thereof'
[patent_app_type] => 1
[patent_app_number] => 7/935339
[patent_app_country] => US
[patent_app_date] => 1992-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/289/05289586.pdf
[firstpage_image] =>[orig_patent_app_number] => 935339
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/935339 | Digital information transmission apparatus and method of driving information transmission bus system thereof | Aug 26, 1992 | Issued |
| 07/933865 | MULTI-PROCESSOR WITH CROSSBAR LINK OF PROCESSORS AND MEMORIES AND METHOD OF OPERATION | Aug 20, 1992 | Abandoned |
Array
(
[id] => 3070111
[patent_doc_number] => 05339394
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-08-16
[patent_title] => 'I/O register protection circuit'
[patent_app_type] => 1
[patent_app_number] => 7/924357
[patent_app_country] => US
[patent_app_date] => 1992-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 17
[patent_no_of_words] => 7707
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/339/05339394.pdf
[firstpage_image] =>[orig_patent_app_number] => 924357
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/924357 | I/O register protection circuit | Jul 30, 1992 | Issued |
Array
(
[id] => 2980003
[patent_doc_number] => 05202965
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-04-13
[patent_title] => 'Electronic system with a plurality of removable units'
[patent_app_type] => 1
[patent_app_number] => 7/919383
[patent_app_country] => US
[patent_app_date] => 1992-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 5904
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 227
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/202/05202965.pdf
[firstpage_image] =>[orig_patent_app_number] => 919383
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/919383 | Electronic system with a plurality of removable units | Jul 28, 1992 | Issued |
Array
(
[id] => 2915711
[patent_doc_number] => 05249285
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-09-28
[patent_title] => 'RAM lock device and method for a text entry system'
[patent_app_type] => 1
[patent_app_number] => 7/919133
[patent_app_country] => US
[patent_app_date] => 1992-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4296
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 171
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/249/05249285.pdf
[firstpage_image] =>[orig_patent_app_number] => 919133
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/919133 | RAM lock device and method for a text entry system | Jul 22, 1992 | Issued |
| 07/914531 | INTERFACE UNIT FOR ENCLOSED ELECTRONIC EQUIPMENT | Jul 16, 1992 | Abandoned |
| 07/915150 | UNIVERSAL ADDRESS GENERATOR | Jul 16, 1992 | Abandoned |
Array
(
[id] => 2951652
[patent_doc_number] => 05261084
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-11-09
[patent_title] => 'Error judgment method'
[patent_app_type] => 1
[patent_app_number] => 7/911792
[patent_app_country] => US
[patent_app_date] => 1992-07-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1889
[patent_no_of_claims] => 1
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[patent_words_short_claim] => 220
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/261/05261084.pdf
[firstpage_image] =>[orig_patent_app_number] => 911792
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/911792 | Error judgment method | Jul 9, 1992 | Issued |
| 07/907493 | MODULAR DATA/CONTROL EQUIPMENT | Jun 30, 1992 | Abandoned |
Array
(
[id] => 2904996
[patent_doc_number] => 05210843
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-05-11
[patent_title] => 'Pseudo set-associative memory caching arrangement'
[patent_app_type] => 1
[patent_app_number] => 7/902805
[patent_app_country] => US
[patent_app_date] => 1992-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 4249
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 90
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/210/05210843.pdf
[firstpage_image] =>[orig_patent_app_number] => 902805
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/902805 | Pseudo set-associative memory caching arrangement | Jun 23, 1992 | Issued |
| 07/901565 | METHOD AND APPARATUS FOR USING ADDRESS TRANSITION DETECTION TO REDUCE POWER CONSUMPTION | Jun 18, 1992 | Abandoned |
Array
(
[id] => 3075850
[patent_doc_number] => 05353235
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-10-04
[patent_title] => 'Wire length minimization in channel compactor'
[patent_app_type] => 1
[patent_app_number] => 7/900030
[patent_app_country] => US
[patent_app_date] => 1992-06-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 12
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/353/05353235.pdf
[firstpage_image] =>[orig_patent_app_number] => 900030
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/900030 | Wire length minimization in channel compactor | Jun 16, 1992 | Issued |
| 07/892809 | DATA BUS SYSTEMS | Jun 4, 1992 | Abandoned |
Array
(
[id] => 3023793
[patent_doc_number] => 05333279
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-07-26
[patent_title] => 'Self-timed mesh routing chip with data broadcasting'
[patent_app_type] => 1
[patent_app_number] => 7/892535
[patent_app_country] => US
[patent_app_date] => 1992-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[pdf_file] => patents/05/333/05333279.pdf
[firstpage_image] =>[orig_patent_app_number] => 892535
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/892535 | Self-timed mesh routing chip with data broadcasting | May 31, 1992 | Issued |
| 07/890406 | METHOD AND APPARATUS FOR INTERRUPT HANDLING IN A MULTI-THREADED OPERATING SYSTEM KERNEL | May 28, 1992 | Abandoned |