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Debra Chun

Examiner (ID: 11282)

Most Active Art Unit
2308
Art Unit(s)
2308, 2307
Total Applications
364
Issued Applications
277
Pending Applications
0
Abandoned Applications
87

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3035151 [patent_doc_number] => 05327539 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-05 [patent_title] => 'Access processing system in information processor' [patent_app_type] => 1 [patent_app_number] => 7/841477 [patent_app_country] => US [patent_app_date] => 1992-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 6506 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/327/05327539.pdf [firstpage_image] =>[orig_patent_app_number] => 841477 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/841477
Access processing system in information processor Feb 25, 1992 Issued
Array ( [id] => 2977669 [patent_doc_number] => 05274828 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-28 [patent_title] => 'Computer including an integrated circuit having an on-chip high voltage source' [patent_app_type] => 1 [patent_app_number] => 7/840419 [patent_app_country] => US [patent_app_date] => 1992-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3856 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/274/05274828.pdf [firstpage_image] =>[orig_patent_app_number] => 840419 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/840419
Computer including an integrated circuit having an on-chip high voltage source Feb 23, 1992 Issued
Array ( [id] => 3084951 [patent_doc_number] => 05337413 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-09 [patent_title] => 'Environment monitoring system for standard interface bus computer systems' [patent_app_type] => 1 [patent_app_number] => 7/831951 [patent_app_country] => US [patent_app_date] => 1992-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4368 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/337/05337413.pdf [firstpage_image] =>[orig_patent_app_number] => 831951 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/831951
Environment monitoring system for standard interface bus computer systems Feb 5, 1992 Issued
07/830305 MULTIPROCESSOR CIRCUIT Jan 30, 1992 Abandoned
07/825743 MULTIPLE INPUT BUFFERS FOR ADDRESS BITS Jan 22, 1992 Abandoned
Array ( [id] => 2958578 [patent_doc_number] => 05255376 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-10-19 [patent_title] => 'Method and apparatus for supporting a dual bit length protocol for data transfers' [patent_app_type] => 1 [patent_app_number] => 7/820561 [patent_app_country] => US [patent_app_date] => 1992-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5683 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 491 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/255/05255376.pdf [firstpage_image] =>[orig_patent_app_number] => 820561 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/820561
Method and apparatus for supporting a dual bit length protocol for data transfers Jan 13, 1992 Issued
Array ( [id] => 3023758 [patent_doc_number] => 05333277 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-26 [patent_title] => 'Data buss interface and expansion system' [patent_app_type] => 1 [patent_app_number] => 7/819202 [patent_app_country] => US [patent_app_date] => 1992-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 31 [patent_no_of_words] => 12425 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/333/05333277.pdf [firstpage_image] =>[orig_patent_app_number] => 819202 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/819202
Data buss interface and expansion system Jan 9, 1992 Issued
Array ( [id] => 3094864 [patent_doc_number] => 05280592 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-18 [patent_title] => 'Domain interlock' [patent_app_type] => 1 [patent_app_number] => 7/816801 [patent_app_country] => US [patent_app_date] => 1992-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 9753 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/280/05280592.pdf [firstpage_image] =>[orig_patent_app_number] => 816801 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/816801
Domain interlock Jan 2, 1992 Issued
Array ( [id] => 2958538 [patent_doc_number] => 05255374 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-10-19 [patent_title] => 'Bus interface logic for computer system having dual bus architecture' [patent_app_type] => 1 [patent_app_number] => 7/816203 [patent_app_country] => US [patent_app_date] => 1992-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7696 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/255/05255374.pdf [firstpage_image] =>[orig_patent_app_number] => 816203 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/816203
Bus interface logic for computer system having dual bus architecture Jan 1, 1992 Issued
Array ( [id] => 2976855 [patent_doc_number] => 05265211 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-23 [patent_title] => 'Arbitration control logic for computer system having dual bus architecture' [patent_app_type] => 1 [patent_app_number] => 7/816116 [patent_app_country] => US [patent_app_date] => 1992-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8185 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/265/05265211.pdf [firstpage_image] =>[orig_patent_app_number] => 816116 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/816116
Arbitration control logic for computer system having dual bus architecture Jan 1, 1992 Issued
07/811708 BUS TERMINATING CIRCUIT Dec 19, 1991 Abandoned
Array ( [id] => 3107477 [patent_doc_number] => 05313626 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-17 [patent_title] => 'Disk drive array with efficient background rebuilding' [patent_app_type] => 1 [patent_app_number] => 7/808841 [patent_app_country] => US [patent_app_date] => 1991-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 31501 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/313/05313626.pdf [firstpage_image] =>[orig_patent_app_number] => 808841 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/808841
Disk drive array with efficient background rebuilding Dec 16, 1991 Issued
Array ( [id] => 2915693 [patent_doc_number] => 05249284 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-28 [patent_title] => 'Method and system for maintaining data coherency between main and cache memories' [patent_app_type] => 1 [patent_app_number] => 7/807428 [patent_app_country] => US [patent_app_date] => 1991-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2993 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/249/05249284.pdf [firstpage_image] =>[orig_patent_app_number] => 807428 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/807428
Method and system for maintaining data coherency between main and cache memories Dec 12, 1991 Issued
Array ( [id] => 3431919 [patent_doc_number] => RE034850 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-07 [patent_title] => 'Digital signal processor' [patent_app_type] => 2 [patent_app_number] => 7/803457 [patent_app_country] => US [patent_app_date] => 1991-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4604 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/034/RE034850.pdf [firstpage_image] =>[orig_patent_app_number] => 803457 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/803457
Digital signal processor Dec 5, 1991 Issued
07/802539 DATA TRANSFER CONTROL SYSTEM Dec 4, 1991 Abandoned
Array ( [id] => 2925838 [patent_doc_number] => 05237698 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-17 [patent_title] => 'Microcomputer' [patent_app_type] => 1 [patent_app_number] => 7/802041 [patent_app_country] => US [patent_app_date] => 1991-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2905 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/237/05237698.pdf [firstpage_image] =>[orig_patent_app_number] => 802041 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/802041
Microcomputer Dec 2, 1991 Issued
Array ( [id] => 2988625 [patent_doc_number] => 05226141 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-06 [patent_title] => 'Variable capacity cache memory' [patent_app_type] => 1 [patent_app_number] => 7/794689 [patent_app_country] => US [patent_app_date] => 1991-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4455 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/226/05226141.pdf [firstpage_image] =>[orig_patent_app_number] => 794689 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/794689
Variable capacity cache memory Nov 17, 1991 Issued
Array ( [id] => 2972043 [patent_doc_number] => 05264958 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-23 [patent_title] => 'Universal communications interface adaptable for a plurality of interface standards' [patent_app_type] => 1 [patent_app_number] => 7/790050 [patent_app_country] => US [patent_app_date] => 1991-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3690 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/264/05264958.pdf [firstpage_image] =>[orig_patent_app_number] => 790050 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/790050
Universal communications interface adaptable for a plurality of interface standards Nov 11, 1991 Issued
07/786461 METHOD FOR EFFICIENT SERIALIZED TRANSMISSION OF HANDSHAKE SIGNAL ON A DIGITAL BUS Nov 9, 1991 Abandoned
07/789168 INTERRUPT CONTROLLER CAPABLE OF DESIGNATING PRIORITY LEVEL Nov 3, 1991 Abandoned
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