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Debra Chun

Examiner (ID: 11282)

Most Active Art Unit
2308
Art Unit(s)
2308, 2307
Total Applications
364
Issued Applications
277
Pending Applications
0
Abandoned Applications
87

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2817589 [patent_doc_number] => 05146605 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-08 [patent_title] => 'Direct control facility for multiprocessor network' [patent_app_type] => 1 [patent_app_number] => 7/644799 [patent_app_country] => US [patent_app_date] => 1991-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5410 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/146/05146605.pdf [firstpage_image] =>[orig_patent_app_number] => 644799 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/644799
Direct control facility for multiprocessor network Jan 22, 1991 Issued
Array ( [id] => 2934187 [patent_doc_number] => 05235686 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-10 [patent_title] => 'Computer system having mixed macrocode and microcode' [patent_app_type] => 1 [patent_app_number] => 7/630728 [patent_app_country] => US [patent_app_date] => 1990-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5023 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/235/05235686.pdf [firstpage_image] =>[orig_patent_app_number] => 630728 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/630728
Computer system having mixed macrocode and microcode Dec 19, 1990 Issued
Array ( [id] => 2888969 [patent_doc_number] => 05185878 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-02-09 [patent_title] => 'Programmable cache memory as well as system incorporating same and method of operating programmable cache memory' [patent_app_type] => 1 [patent_app_number] => 7/626239 [patent_app_country] => US [patent_app_date] => 1990-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 27318 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/185/05185878.pdf [firstpage_image] =>[orig_patent_app_number] => 626239 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/626239
Programmable cache memory as well as system incorporating same and method of operating programmable cache memory Dec 11, 1990 Issued
Array ( [id] => 3063193 [patent_doc_number] => 05305439 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-19 [patent_title] => 'Method and apparatus for time-shared processing of different data word sequences' [patent_app_type] => 1 [patent_app_number] => 7/616448 [patent_app_country] => US [patent_app_date] => 1990-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4467 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/305/05305439.pdf [firstpage_image] =>[orig_patent_app_number] => 616448 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/616448
Method and apparatus for time-shared processing of different data word sequences Nov 19, 1990 Issued
07/612773 ELASTIC CONFIGURABLE BUFFER FOR BUFFERING ASYNCHRONOUS DATA Nov 12, 1990 Abandoned
07/611141 MULTIPLE MICROCONTROLLER HARD DISK DRIVE CONTROL ARCHITECTURE Nov 8, 1990 Abandoned
07/603362 PROGRAMMABLE CONTROLLER HAVING A MEANS TO ACCEPT A PLURALITY OF I/O DEVICES MOUNTABLE IN ARBITRARY SLOTS Oct 25, 1990 Abandoned
07/600140 FAIR ARBITRATION SCHEME Oct 16, 1990 Abandoned
Array ( [id] => 3025116 [patent_doc_number] => 05276886 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-04 [patent_title] => 'Hardware semaphores in a multi-processor environment' [patent_app_type] => 1 [patent_app_number] => 7/596101 [patent_app_country] => US [patent_app_date] => 1990-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2036 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/276/05276886.pdf [firstpage_image] =>[orig_patent_app_number] => 596101 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/596101
Hardware semaphores in a multi-processor environment Oct 10, 1990 Issued
Array ( [id] => 2911009 [patent_doc_number] => 05218539 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-06-08 [patent_title] => 'Forms processor with controlled remote revision' [patent_app_type] => 1 [patent_app_number] => 7/595740 [patent_app_country] => US [patent_app_date] => 1990-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 4378 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/218/05218539.pdf [firstpage_image] =>[orig_patent_app_number] => 595740 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/595740
Forms processor with controlled remote revision Oct 9, 1990 Issued
Array ( [id] => 2733635 [patent_doc_number] => 05057998 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-10-15 [patent_title] => 'Data transfer control unit' [patent_app_type] => 1 [patent_app_number] => 7/593600 [patent_app_country] => US [patent_app_date] => 1990-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3099 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/057/05057998.pdf [firstpage_image] =>[orig_patent_app_number] => 593600 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/593600
Data transfer control unit Oct 3, 1990 Issued
Array ( [id] => 3107785 [patent_doc_number] => 05313642 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-17 [patent_title] => 'Power interface for peripheral devices' [patent_app_type] => 1 [patent_app_number] => 7/592212 [patent_app_country] => US [patent_app_date] => 1990-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 8116 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/313/05313642.pdf [firstpage_image] =>[orig_patent_app_number] => 592212 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/592212
Power interface for peripheral devices Oct 2, 1990 Issued
Array ( [id] => 2742876 [patent_doc_number] => 05077658 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-12-31 [patent_title] => 'Data access system for a file access processor' [patent_app_type] => 1 [patent_app_number] => 7/593278 [patent_app_country] => US [patent_app_date] => 1990-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9353 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 486 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/077/05077658.pdf [firstpage_image] =>[orig_patent_app_number] => 593278 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/593278
Data access system for a file access processor Sep 20, 1990 Issued
Array ( [id] => 2931126 [patent_doc_number] => 05206952 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-27 [patent_title] => 'Fault tolerant networking architecture' [patent_app_type] => 1 [patent_app_number] => 7/582507 [patent_app_country] => US [patent_app_date] => 1990-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3956 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/206/05206952.pdf [firstpage_image] =>[orig_patent_app_number] => 582507 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/582507
Fault tolerant networking architecture Sep 11, 1990 Issued
Array ( [id] => 2844004 [patent_doc_number] => 05129081 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-07 [patent_title] => 'System for processing data using logic language' [patent_app_type] => 1 [patent_app_number] => 7/579249 [patent_app_country] => US [patent_app_date] => 1990-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1269 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/129/05129081.pdf [firstpage_image] =>[orig_patent_app_number] => 579249 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/579249
System for processing data using logic language Sep 5, 1990 Issued
Array ( [id] => 2913782 [patent_doc_number] => 05218681 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-06-08 [patent_title] => 'Apparatus for controlling access to a data bus' [patent_app_type] => 1 [patent_app_number] => 7/576061 [patent_app_country] => US [patent_app_date] => 1990-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3443 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 414 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/218/05218681.pdf [firstpage_image] =>[orig_patent_app_number] => 576061 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/576061
Apparatus for controlling access to a data bus Aug 30, 1990 Issued
Array ( [id] => 2799036 [patent_doc_number] => 05155814 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-10-13 [patent_title] => 'Nonsynchronous channel/DASD communication system' [patent_app_type] => 1 [patent_app_number] => 7/575735 [patent_app_country] => US [patent_app_date] => 1990-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5923 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/155/05155814.pdf [firstpage_image] =>[orig_patent_app_number] => 575735 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/575735
Nonsynchronous channel/DASD communication system Aug 30, 1990 Issued
07/576569 NOTIFICATION AND VERIFICATION OF STATE CHANGES IN A DATA PROCESSING INPUT/OUTPUT SYSTEM Aug 30, 1990 Abandoned
Array ( [id] => 2949019 [patent_doc_number] => 05247687 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-21 [patent_title] => 'Method and apparatus for determining and using program paging characteristics to optimize system productive CPU time' [patent_app_type] => 1 [patent_app_number] => 7/576539 [patent_app_country] => US [patent_app_date] => 1990-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 25 [patent_no_of_words] => 11106 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/247/05247687.pdf [firstpage_image] =>[orig_patent_app_number] => 576539 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/576539
Method and apparatus for determining and using program paging characteristics to optimize system productive CPU time Aug 30, 1990 Issued
Array ( [id] => 2819783 [patent_doc_number] => 05157770 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-10-20 [patent_title] => 'Nonsynchronous DASD control' [patent_app_type] => 1 [patent_app_number] => 7/575741 [patent_app_country] => US [patent_app_date] => 1990-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 4062 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/157/05157770.pdf [firstpage_image] =>[orig_patent_app_number] => 575741 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/575741
Nonsynchronous DASD control Aug 30, 1990 Issued
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