Search

Deepak R. Rao

Examiner (ID: 9276, Phone: (571)272-0672 , Office: P/1624 )

Most Active Art Unit
1624
Art Unit(s)
1624, 1611, 1202
Total Applications
3005
Issued Applications
2150
Pending Applications
168
Abandoned Applications
701

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17018203 [patent_doc_number] => 11087848 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-08-10 [patent_title] => Data arranging method, memory control circuit unit and memory storage device for flash memory for improving the performance of valid data merging operation [patent_app_type] => utility [patent_app_number] => 16/812373 [patent_app_country] => US [patent_app_date] => 2020-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 7363 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16812373 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/812373
Data arranging method, memory control circuit unit and memory storage device for flash memory for improving the performance of valid data merging operation Mar 8, 2020 Issued
Array ( [id] => 16928083 [patent_doc_number] => 11049572 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-06-29 [patent_title] => Memory device, source line voltage adjuster and source line voltage adjusting method thereof [patent_app_type] => utility [patent_app_number] => 16/811896 [patent_app_country] => US [patent_app_date] => 2020-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3619 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16811896 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/811896
Memory device, source line voltage adjuster and source line voltage adjusting method thereof Mar 5, 2020 Issued
Array ( [id] => 16624591 [patent_doc_number] => 20210043244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => MEMORY DEVICE HAVING DIFFERENT NUMBERS OF BITS STORED IN MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 16/810527 [patent_app_country] => US [patent_app_date] => 2020-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12289 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16810527 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/810527
Memory device having different numbers of bits stored in memory cells Mar 4, 2020 Issued
Array ( [id] => 16660369 [patent_doc_number] => 20210057006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-25 [patent_title] => SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 16/806822 [patent_app_country] => US [patent_app_date] => 2020-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4867 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16806822 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/806822
Semiconductor device and semiconductor system including the same Mar 1, 2020 Issued
Array ( [id] => 17018198 [patent_doc_number] => 11087843 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-08-10 [patent_title] => Memory with FRAM and SRAM of IC and method for accessing memory [patent_app_type] => utility [patent_app_number] => 16/785997 [patent_app_country] => US [patent_app_date] => 2020-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 6806 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16785997 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/785997
Memory with FRAM and SRAM of IC and method for accessing memory Feb 9, 2020 Issued
Array ( [id] => 16803088 [patent_doc_number] => 10998039 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-05-04 [patent_title] => Apparatuses, systems, and methods for latch reset logic [patent_app_type] => utility [patent_app_number] => 16/785338 [patent_app_country] => US [patent_app_date] => 2020-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8304 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16785338 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/785338
Apparatuses, systems, and methods for latch reset logic Feb 6, 2020 Issued
Array ( [id] => 15806935 [patent_doc_number] => 20200126610 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-23 [patent_title] => NONVOLATILE MEMORY STRUCTURES WITH DRAM [patent_app_type] => utility [patent_app_number] => 16/720082 [patent_app_country] => US [patent_app_date] => 2019-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7629 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16720082 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/720082
Nonvolatile memory structures with dram Dec 18, 2019 Issued
Array ( [id] => 16699707 [patent_doc_number] => 10950315 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-16 [patent_title] => Preread and read threshold voltage optimization [patent_app_type] => utility [patent_app_number] => 16/715639 [patent_app_country] => US [patent_app_date] => 2019-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10382 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16715639 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/715639
Preread and read threshold voltage optimization Dec 15, 2019 Issued
Array ( [id] => 15775201 [patent_doc_number] => 20200118618 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => Memory Array with Bit-Lines Connected to Different Sub-Arrays Through Jumper Structures [patent_app_type] => utility [patent_app_number] => 16/710383 [patent_app_country] => US [patent_app_date] => 2019-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5143 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16710383 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/710383
Memory array with bit-lines connected to different sub-arrays through jumper structures Dec 10, 2019 Issued
Array ( [id] => 15624923 [patent_doc_number] => 20200082866 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-12 [patent_title] => INTEGRATED CIRCUIT MEMORY DEVICE AND METHOD OF OPERATING SAME [patent_app_type] => utility [patent_app_number] => 16/688481 [patent_app_country] => US [patent_app_date] => 2019-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7489 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16688481 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/688481
Integrated circuit memory device and method of operating same Nov 18, 2019 Issued
Array ( [id] => 15658377 [patent_doc_number] => 20200091719 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-19 [patent_title] => Systems and Methods for Utilization of Demand Side Assets for Provision of Grid Services [patent_app_type] => utility [patent_app_number] => 16/686928 [patent_app_country] => US [patent_app_date] => 2019-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2128 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16686928 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/686928
Systems and methods for utilization of demand side assets for provision of grid services Nov 17, 2019 Issued
Array ( [id] => 16943922 [patent_doc_number] => 11056170 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-06 [patent_title] => Semiconductor device providing an output in response to a read command or a mode-register read command [patent_app_type] => utility [patent_app_number] => 16/685914 [patent_app_country] => US [patent_app_date] => 2019-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3377 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16685914 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/685914
Semiconductor device providing an output in response to a read command or a mode-register read command Nov 14, 2019 Issued
Array ( [id] => 15597067 [patent_doc_number] => 20200075068 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-05 [patent_title] => MEMORY DEVICES WITH IMPROVED REFRESHING OPERATION [patent_app_type] => utility [patent_app_number] => 16/676290 [patent_app_country] => US [patent_app_date] => 2019-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3943 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16676290 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/676290
Memory devices with improved refreshing operation Nov 5, 2019 Issued
Array ( [id] => 17092680 [patent_doc_number] => 11120874 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-14 [patent_title] => Electronic memory device and a method of manipulating the electronic memory device [patent_app_type] => utility [patent_app_number] => 16/671669 [patent_app_country] => US [patent_app_date] => 2019-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 4695 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 300 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16671669 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/671669
Electronic memory device and a method of manipulating the electronic memory device Oct 31, 2019 Issued
Array ( [id] => 15563801 [patent_doc_number] => 20200066312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-27 [patent_title] => MEMORY CIRCUIT AND METHOD OF OPERATING A MEMORY CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/666425 [patent_app_country] => US [patent_app_date] => 2019-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9475 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16666425 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/666425
Memory circuit and method of operating a memory circuit Oct 28, 2019 Issued
Array ( [id] => 16865596 [patent_doc_number] => 11024347 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-01 [patent_title] => Multiple sense amplifier and data path-based pseudo dual port SRAM [patent_app_type] => utility [patent_app_number] => 16/655283 [patent_app_country] => US [patent_app_date] => 2019-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6441 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16655283 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/655283
Multiple sense amplifier and data path-based pseudo dual port SRAM Oct 16, 2019 Issued
Array ( [id] => 16479332 [patent_doc_number] => 10854285 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-01 [patent_title] => Memory access module for performing a plurality of sensing operations to generate digital values of a storage cell in order to perform decoding of the storage cell [patent_app_type] => utility [patent_app_number] => 16/656533 [patent_app_country] => US [patent_app_date] => 2019-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 10288 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16656533 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/656533
Memory access module for performing a plurality of sensing operations to generate digital values of a storage cell in order to perform decoding of the storage cell Oct 16, 2019 Issued
Array ( [id] => 16715375 [patent_doc_number] => 20210082522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => VOLTAGE IDENTIFYING METHOD, MEMORY CONTROLLING CIRCUIT UNIT AND MEMORY STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 16/601517 [patent_app_country] => US [patent_app_date] => 2019-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10086 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16601517 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/601517
Voltage identifying method, memory controlling circuit unit and memory storage device Oct 13, 2019 Issued
Array ( [id] => 16347734 [patent_doc_number] => 20200312385 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => MEMORY HAVING BIT LINE SENSE AMPLIFIER [patent_app_type] => utility [patent_app_number] => 16/597317 [patent_app_country] => US [patent_app_date] => 2019-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4192 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16597317 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/597317
Memory having bit line sense amplifier Oct 8, 2019 Issued
Array ( [id] => 16845736 [patent_doc_number] => 11017829 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-25 [patent_title] => Magnetic memory device including voltage generator connected to both word line driver and write driver [patent_app_type] => utility [patent_app_number] => 16/582273 [patent_app_country] => US [patent_app_date] => 2019-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7767 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16582273 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/582273
Magnetic memory device including voltage generator connected to both word line driver and write driver Sep 24, 2019 Issued
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