
Deepak R. Rao
Examiner (ID: 1911, Phone: (571)272-0672 , Office: P/1624 )
| Most Active Art Unit | 1624 |
| Art Unit(s) | 1624, 1611, 1202 |
| Total Applications | 3005 |
| Issued Applications | 2150 |
| Pending Applications | 168 |
| Abandoned Applications | 701 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 9332319
[patent_doc_number] => 20140059101
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-02-27
[patent_title] => 'OPTIMIZED METHOD OF BIQUAD INFINITE-IMPULSE RESPONSE CALCULATION'
[patent_app_type] => utility
[patent_app_number] => 13/595071
[patent_app_country] => US
[patent_app_date] => 2012-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1641
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13595071
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/595071 | OPTIMIZED METHOD OF BIQUAD INFINITE-IMPULSE RESPONSE CALCULATION | Aug 26, 2012 | Abandoned |
Array
(
[id] => 8686381
[patent_doc_number] => 20130054665
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-02-28
[patent_title] => 'METHODS AND SYSTEMS FOR PERFORMING EXPONENTIATION IN A PARALLEL PROCESSING ENVIRONMENT'
[patent_app_type] => utility
[patent_app_number] => 13/594166
[patent_app_country] => US
[patent_app_date] => 2012-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 11515
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13594166
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/594166 | Methods and systems for performing exponentiation in a parallel processing environment | Aug 23, 2012 | Issued |
Array
(
[id] => 8517752
[patent_doc_number] => 20120317160
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-12-13
[patent_title] => 'MATRIX CALCULATION METHOD, PROGRAM, AND SYSTEM'
[patent_app_type] => utility
[patent_app_number] => 13/591631
[patent_app_country] => US
[patent_app_date] => 2012-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 6397
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13591631
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/591631 | Matrix calculation method, program, and system | Aug 21, 2012 | Issued |
Array
(
[id] => 10894811
[patent_doc_number] => 08918442
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-12-23
[patent_title] => 'Reducing bias in hardware generated random numbers'
[patent_app_type] => utility
[patent_app_number] => 13/592295
[patent_app_country] => US
[patent_app_date] => 2012-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 8752
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13592295
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/592295 | Reducing bias in hardware generated random numbers | Aug 21, 2012 | Issued |
Array
(
[id] => 9332313
[patent_doc_number] => 20140059095
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-02-27
[patent_title] => 'SYSTEM AND METHOD FOR MEAN ESTIMATION FOR A TORSO-HEAVY TAIL DISTRIBUTION'
[patent_app_type] => utility
[patent_app_number] => 13/590934
[patent_app_country] => US
[patent_app_date] => 2012-08-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6401
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13590934
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/590934 | SYSTEM AND METHOD FOR MEAN ESTIMATION FOR A TORSO-HEAVY TAIL DISTRIBUTION | Aug 20, 2012 | Abandoned |
Array
(
[id] => 10242699
[patent_doc_number] => 20150127694
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-05-07
[patent_title] => 'GENERATING AND PARTITIONING POLYNOMIALS'
[patent_app_type] => utility
[patent_app_number] => 14/397717
[patent_app_country] => US
[patent_app_date] => 2012-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2305
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14397717
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/397717 | Generating and partitioning polynomials | Jul 29, 2012 | Issued |
Array
(
[id] => 9834286
[patent_doc_number] => 08943115
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2015-01-27
[patent_title] => 'Bitwise comparator for selecting two smallest numbers from a set of numbers'
[patent_app_type] => utility
[patent_app_number] => 13/545652
[patent_app_country] => US
[patent_app_date] => 2012-07-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 3812
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 249
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13545652
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/545652 | Bitwise comparator for selecting two smallest numbers from a set of numbers | Jul 9, 2012 | Issued |
| 13/545263 | IMPLEMENTING LARGE MULTIPLIERS IN A PROGRAMMABLE INTEGRATED CIRCUIT DEVICE | Jul 9, 2012 | Abandoned |
Array
(
[id] => 9825814
[patent_doc_number] => 08935310
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-01-13
[patent_title] => 'Parallel computation of a remainder by division of a sequence of bytes'
[patent_app_type] => utility
[patent_app_number] => 13/495533
[patent_app_country] => US
[patent_app_date] => 2012-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4933
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 525
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13495533
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/495533 | Parallel computation of a remainder by division of a sequence of bytes | Jun 12, 2012 | Issued |
Array
(
[id] => 8443292
[patent_doc_number] => 20120259908
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-10-11
[patent_title] => 'FAST CARRY LOOKAHEAD CIRCUITS'
[patent_app_type] => utility
[patent_app_number] => 13/494850
[patent_app_country] => US
[patent_app_date] => 2012-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4424
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13494850
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/494850 | Fast carry lookahead circuits | Jun 11, 2012 | Issued |
Array
(
[id] => 8372226
[patent_doc_number] => 20120221614
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-08-30
[patent_title] => 'Processor Pipeline which Implements Fused and Unfused Multiply-Add Instructions'
[patent_app_type] => utility
[patent_app_number] => 13/469212
[patent_app_country] => US
[patent_app_date] => 2012-05-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5969
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13469212
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/469212 | Processor pipeline which implements fused and unfused multiply-add instructions | May 10, 2012 | Issued |
Array
(
[id] => 8337111
[patent_doc_number] => 20120203816
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-08-09
[patent_title] => 'Optimized Corner Turns for Local Storage and Bandwidth Reduction'
[patent_app_type] => utility
[patent_app_number] => 13/451967
[patent_app_country] => US
[patent_app_date] => 2012-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6061
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13451967
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/451967 | Optimized corner turns for local storage and bandwidth reduction | Apr 19, 2012 | Issued |
Array
(
[id] => 10550124
[patent_doc_number] => 09274750
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-03-01
[patent_title] => 'System and method for signal processing in digital signal processors'
[patent_app_type] => utility
[patent_app_number] => 13/452690
[patent_app_country] => US
[patent_app_date] => 2012-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 7995
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 188
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13452690
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/452690 | System and method for signal processing in digital signal processors | Apr 19, 2012 | Issued |
Array
(
[id] => 9385885
[patent_doc_number] => 20140089368
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-03-27
[patent_title] => 'Device with capability of processing FFT radix 2 butterfly operation and operation method thereof'
[patent_app_type] => utility
[patent_app_number] => 14/115340
[patent_app_country] => US
[patent_app_date] => 2012-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2953
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14115340
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/115340 | Device with capability of processing FFT radix 2 butterfly operation and operation method thereof | Apr 19, 2012 | Issued |
Array
(
[id] => 8443288
[patent_doc_number] => 20120259903
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-10-11
[patent_title] => 'ARITHMETIC CIRCUIT, ARITHMETIC PROCESSING APPARATUS AND METHOD OF CONTROLLING ARITHMETIC CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 13/439932
[patent_app_country] => US
[patent_app_date] => 2012-04-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 43
[patent_figures_cnt] => 43
[patent_no_of_words] => 23158
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13439932
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/439932 | ARITHMETIC CIRCUIT, ARITHMETIC PROCESSING APPARATUS AND METHOD OF CONTROLLING ARITHMETIC CIRCUIT | Apr 4, 2012 | Abandoned |
Array
(
[id] => 9967585
[patent_doc_number] => 09015217
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-04-21
[patent_title] => 'Transcendental and non-linear components using series expansion'
[patent_app_type] => utility
[patent_app_number] => 13/435900
[patent_app_country] => US
[patent_app_date] => 2012-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 16
[patent_no_of_words] => 8676
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 206
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13435900
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/435900 | Transcendental and non-linear components using series expansion | Mar 29, 2012 | Issued |
Array
(
[id] => 9070031
[patent_doc_number] => 20130261787
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-10-03
[patent_title] => 'Optimization of System Control Based on Solving Multi-Point Boundary Value Problems'
[patent_app_type] => utility
[patent_app_number] => 13/434621
[patent_app_country] => US
[patent_app_date] => 2012-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 10154
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13434621
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/434621 | Optimization of system control based on solving multi-point boundary value problems | Mar 28, 2012 | Issued |
Array
(
[id] => 8404906
[patent_doc_number] => 20120236968
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-09-20
[patent_title] => 'ENHANCED LATTICE REDUCTION SYSTEMS AND METHODS'
[patent_app_type] => utility
[patent_app_number] => 13/424079
[patent_app_country] => US
[patent_app_date] => 2012-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 5799
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13424079
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/424079 | Enhanced lattice reduction systems and methods | Mar 18, 2012 | Issued |
Array
(
[id] => 8404906
[patent_doc_number] => 20120236968
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-09-20
[patent_title] => 'ENHANCED LATTICE REDUCTION SYSTEMS AND METHODS'
[patent_app_type] => utility
[patent_app_number] => 13/424079
[patent_app_country] => US
[patent_app_date] => 2012-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 5799
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13424079
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/424079 | Enhanced lattice reduction systems and methods | Mar 18, 2012 | Issued |
Array
(
[id] => 11910545
[patent_doc_number] => 09779359
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-10-03
[patent_title] => 'Quantum arithmetic on two-dimensional quantum architectures'
[patent_app_type] => utility
[patent_app_number] => 13/420247
[patent_app_country] => US
[patent_app_date] => 2012-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 27
[patent_no_of_words] => 10601
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 183
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13420247
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/420247 | Quantum arithmetic on two-dimensional quantum architectures | Mar 13, 2012 | Issued |