
Deepak R. Rao
Examiner (ID: 9276, Phone: (571)272-0672 , Office: P/1624 )
| Most Active Art Unit | 1624 |
| Art Unit(s) | 1624, 1611, 1202 |
| Total Applications | 3005 |
| Issued Applications | 2150 |
| Pending Applications | 168 |
| Abandoned Applications | 701 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7211520
[patent_doc_number] => 20050259493
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[patent_issue_date] => 2005-11-24
[patent_title] => 'Method and system for controlling refresh in volatile memories'
[patent_app_type] => utility
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[patent_app_country] => US
[patent_app_date] => 2005-02-10
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Array
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[patent_title] => 'Semiconductor memory device and method of refreshing the semiconductor memory device'
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Array
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[patent_issue_date] => 2005-07-14
[patent_title] => 'Match line sensing amplifier for content addressable memory'
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Array
(
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[patent_issue_date] => 2006-08-15
[patent_title] => 'CAM memory architecture and a method of forming and operating a device according to a CAM memory architecture'
[patent_app_type] => utility
[patent_app_number] => 11/034720
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/034720 | CAM memory architecture and a method of forming and operating a device according to a CAM memory architecture | Jan 13, 2005 | Issued |
| 11/032792 | Programmable matrix array with phase-change material | Jan 10, 2005 | Abandoned |
Array
(
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[patent_title] => 'Method for programming multi-level nitride read-only memory cells'
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Array
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Array
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[patent_title] => 'Reducing floating gate to floating gate coupling effect'
[patent_app_type] => utility
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Array
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[patent_title] => 'Flash memory devices having power level detection circuits'
[patent_app_type] => utility
[patent_app_number] => 11/020900
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[firstpage_image] =>[orig_patent_app_number] => 11020900
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/020900 | Flash memory devices having power level detection circuits | Dec 22, 2004 | Issued |
Array
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Array
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[patent_title] => 'Semiconductor memory device with a stacked gate including a floating gate and a control gate'
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Array
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[patent_title] => 'METHODS FOR ENHANCING PERFORMANCE OF FERROELECTRIC MEMORY WITH POLARIZATION TREATMENT'
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Array
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Array
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Array
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Array
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Array
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