Delia M. Ramirez

Array ( [id] => 7633036 [patent_doc_number] => 06658584 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-02 [patent_title] => 'Method and structure for managing large counter arrays' [patent_app_type] => B1 [patent_app_number] => 09/656556 [patent_app_country] => US [patent_app_date] => 2000-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3253 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/658/06658584.pdf [firstpage_image] =>[orig_patent_app_number] => 09656556 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1229340 [patent_doc_number] => 06701447 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-02 [patent_title] => 'System for delaying the counting of occurrences of a plurality of events occurring in a processor until the disposition of the event has been determined' [patent_app_type] => B1 [patent_app_number] => 09/656547 [patent_app_country] => US [patent_app_date] => 2000-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5540 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/701/06701447.pdf [firstpage_image] =>[orig_patent_app_number] => 09656547 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1184915 [patent_doc_number] => 06748549 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-08 [patent_title] => 'Clocking an I/O buffer, having a selectable phase difference from the system clock, to and from a remote I/O buffer clocked in phase with the system clock' [patent_app_type] => B1 [patent_app_number] => 09/604049 [patent_app_country] => US [patent_app_date] => 2000-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7628 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/748/06748549.pdf [firstpage_image] =>[orig_patent_app_number] => 09604049 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1314738 [patent_doc_number] => 06622254 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-16 [patent_title] => 'Method of automatically overclocking central processing units' [patent_app_type] => B1 [patent_app_number] => 09/577682 [patent_app_country] => US [patent_app_date] => 2000-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1515 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/622/06622254.pdf [firstpage_image] =>[orig_patent_app_number] => 09577682 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1309113 [patent_doc_number] => 06629255 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-30 [patent_title] => 'Generating a 2-phase clock using a non-50% divider circuit' [patent_app_type] => B1 [patent_app_number] => 09/576943 [patent_app_country] => US [patent_app_date] => 2000-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2846 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/629/06629255.pdf [firstpage_image] =>[orig_patent_app_number] => 09576943 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1297334 [patent_doc_number] => 06633991 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-14 [patent_title] => 'Method of switching between a first and second clock signal by establishing a trigger time in which both signals are considered to be substantially in-phase' [patent_app_type] => B1 [patent_app_number] => 09/572170 [patent_app_country] => US [patent_app_date] => 2000-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4210 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/633/06633991.pdf [firstpage_image] =>[orig_patent_app_number] => 09572170 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7631528 [patent_doc_number] => 06665809 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-16 [patent_title] => 'Digital frequency correction' [patent_app_type] => B1 [patent_app_number] => 09/573015 [patent_app_country] => US [patent_app_date] => 2000-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4094 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/665/06665809.pdf [firstpage_image] =>[orig_patent_app_number] => 09573015 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7629960 [patent_doc_number] => 06636979 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-21 [patent_title] => 'System for measuring phase error between two clocks by using a plurality of phase latches with different respective delays' [patent_app_type] => B1 [patent_app_number] => 09/548507 [patent_app_country] => US [patent_app_date] => 2000-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3966 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/636/06636979.pdf [firstpage_image] =>[orig_patent_app_number] => 09548507 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1292189 [patent_doc_number] => 06643791 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-04 [patent_title] => 'Clock distribution scheme in a signaling server' [patent_app_type] => B1 [patent_app_number] => 09/541002 [patent_app_country] => US [patent_app_date] => 2000-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 63 [patent_no_of_words] => 14135 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/643/06643791.pdf [firstpage_image] =>[orig_patent_app_number] => 09541002 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1353640 [patent_doc_number] => 06594767 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-15 [patent_title] => 'System for preventing power save mode during a pre-set condition while tracking patterns of use in order to modify the pre-set condition to accommodate the patterns of use' [patent_app_type] => B1 [patent_app_number] => 09/541106 [patent_app_country] => US [patent_app_date] => 2000-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2022 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/594/06594767.pdf [firstpage_image] =>[orig_patent_app_number] => 09541106 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1311512 [patent_doc_number] => 06625730 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-23 [patent_title] => 'System for validating a bios program and memory coupled therewith by using a boot block program having a validation routine' [patent_app_type] => B1 [patent_app_number] => 09/540812 [patent_app_country] => US [patent_app_date] => 2000-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 7518 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/625/06625730.pdf [firstpage_image] =>[orig_patent_app_number] => 09540812 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1297353 [patent_doc_number] => 06633995 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-14 [patent_title] => 'System for generating N pipeline control signals by delaying at least one control signal corresponding to a subsequent data path circuit' [patent_app_type] => B1 [patent_app_number] => 09/522310 [patent_app_country] => US [patent_app_date] => 2000-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4734 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/633/06633995.pdf [firstpage_image] =>[orig_patent_app_number] => 09522310 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1357409 [patent_doc_number] => 06591371 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-08 [patent_title] => 'System for counting a number of clock cycles such that a count signal is diverted from a cascaded series of write latches to a cascaded series of erase latches' [patent_app_type] => B1 [patent_app_number] => 09/483863 [patent_app_country] => US [patent_app_date] => 2000-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4160 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/591/06591371.pdf [firstpage_image] =>[orig_patent_app_number] => 09483863 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1365651 [patent_doc_number] => 06581165 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-17 [patent_title] => 'System for asynchronously transferring timed data using first and second clock signals for reading and writing respectively when both clock signals maintaining predetermined phase offset' [patent_app_type] => B1 [patent_app_number] => 09/483520 [patent_app_country] => US [patent_app_date] => 2000-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5303 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/581/06581165.pdf [firstpage_image] =>[orig_patent_app_number] => 09483520 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1409736 [patent_doc_number] => 06557099 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-29 [patent_title] => 'Multiprocessor system for distributively determining the identity of a new control processor based upon the identity of the failing processor(s) stored therein' [patent_app_type] => B1 [patent_app_number] => 09/476733 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 9464 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/557/06557099.pdf [firstpage_image] =>[orig_patent_app_number] => 09476733 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1425495 [patent_doc_number] => 06535989 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-18 [patent_title] => 'Input clock delayed by a plurality of elements that are connected to logic circuitry to produce a clock frequency having a rational multiple less than one' [patent_app_type] => B1 [patent_app_number] => 09/471462 [patent_app_country] => US [patent_app_date] => 1999-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 3799 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/535/06535989.pdf [firstpage_image] =>[orig_patent_app_number] => 09471462 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1412204 [patent_doc_number] => 06553502 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Graphics user interface for power optimization diagnostics' [patent_app_type] => B1 [patent_app_number] => 09/464056 [patent_app_country] => US [patent_app_date] => 1999-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 30 [patent_no_of_words] => 6120 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/553/06553502.pdf [firstpage_image] =>[orig_patent_app_number] => 09464056 [rel_patent_id] =>[rel_patent_doc_number] =>)