Demetrios C. Kerveros

Array ( [id] => 20403839 [patent_doc_number] => 12493815 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-09 [patent_title] => Quantum error correction with runtime trigger events [patent_app_type] => utility [patent_app_number] => 19/044864 [patent_app_country] => US [patent_app_date] => 2025-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6800 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19044864 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19603305 [patent_doc_number] => 20240394185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => POWER LOSS PROTECTION IN MEMORY SUB-SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/793458 [patent_app_country] => US [patent_app_date] => 2024-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7265 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18793458 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19559667 [patent_doc_number] => 20240371459 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => EXTERNAL MAGNETIC FIELD DETECTION FOR MRAM DEVICE [patent_app_type] => utility [patent_app_number] => 18/778993 [patent_app_country] => US [patent_app_date] => 2024-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7644 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18778993 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19560854 [patent_doc_number] => 20240372646 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => BASE STATION, TERMINAL AND COMMUNICATION METHOD [patent_app_type] => utility [patent_app_number] => 18/772997 [patent_app_country] => US [patent_app_date] => 2024-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14436 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18772997 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20243956 [patent_doc_number] => 12424286 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Memory system [patent_app_type] => utility [patent_app_number] => 18/768178 [patent_app_country] => US [patent_app_date] => 2024-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 12289 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 357 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18768178 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20243956 [patent_doc_number] => 12424286 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Memory system [patent_app_type] => utility [patent_app_number] => 18/768178 [patent_app_country] => US [patent_app_date] => 2024-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 12289 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 357 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18768178 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19725847 [patent_doc_number] => 20250028598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => MAINTAINING INTEGRITY OF CONFIGURATION DATA FOR MEMORY SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/763967 [patent_app_country] => US [patent_app_date] => 2024-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13191 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18763967 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20322547 [patent_doc_number] => 20250334635 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-30 [patent_title] => CRITICAL PATH SENSITIZATION IN ELECTRONIC SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/744887 [patent_app_country] => US [patent_app_date] => 2024-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8000 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18744887 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19956371 [patent_doc_number] => 12326785 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-10 [patent_title] => Transmission side transmission device and redundancy method of transmission side transmission device [patent_app_type] => utility [patent_app_number] => 18/740683 [patent_app_country] => US [patent_app_date] => 2024-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4336 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18740683 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19695004 [patent_doc_number] => 20250013549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => NARX ARCHITECTURE FOR TASK CONTENTION MODELS USING TIME-SERIES AND FINE-GRAIN INSTRUMENTATION FOR MPSoCs [patent_app_type] => utility [patent_app_number] => 18/740058 [patent_app_country] => US [patent_app_date] => 2024-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7215 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18740058 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20087314 [patent_doc_number] => 20250217250 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => MEMORY DEVICE AND TESTING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/679452 [patent_app_country] => US [patent_app_date] => 2024-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2102 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18679452 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20087314 [patent_doc_number] => 20250217250 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => MEMORY DEVICE AND TESTING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/679452 [patent_app_country] => US [patent_app_date] => 2024-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2102 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18679452 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20380526 [patent_doc_number] => 20250363019 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-27 [patent_title] => Single Voting Processor Architecture [patent_app_type] => utility [patent_app_number] => 18/675078 [patent_app_country] => US [patent_app_date] => 2024-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18675078 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20380526 [patent_doc_number] => 20250363019 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-27 [patent_title] => Single Voting Processor Architecture [patent_app_type] => utility [patent_app_number] => 18/675078 [patent_app_country] => US [patent_app_date] => 2024-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18675078 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19604468 [patent_doc_number] => 20240395348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => MEMORY FAILURE ANALYSIS BASED ON BITLINE THRESHOLD VOLTAGE DISTRIBUTIONS [patent_app_type] => utility [patent_app_number] => 18/662306 [patent_app_country] => US [patent_app_date] => 2024-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10254 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18662306 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20228489 [patent_doc_number] => 12417141 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-16 [patent_title] => Generating a target data based on a function associated with a physical variation of a device [patent_app_type] => utility [patent_app_number] => 18/644084 [patent_app_country] => US [patent_app_date] => 2024-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18644084 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20228489 [patent_doc_number] => 12417141 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-16 [patent_title] => Generating a target data based on a function associated with a physical variation of a device [patent_app_type] => utility [patent_app_number] => 18/644084 [patent_app_country] => US [patent_app_date] => 2024-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18644084 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20019336 [patent_doc_number] => 20250157558 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => INTERACTIVE DRAM SIGNAL ANALYZER AND METHOD OF ANALYZING AND CALIBRATING DRAM SIGNAL USING THE SAME [patent_app_type] => utility [patent_app_number] => 18/641983 [patent_app_country] => US [patent_app_date] => 2024-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18641983 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19362877 [patent_doc_number] => 20240264911 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => DEVICES USING CHIPLET BASED STORAGE ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 18/641141 [patent_app_country] => US [patent_app_date] => 2024-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15779 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18641141 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19362877 [patent_doc_number] => 20240264911 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => DEVICES USING CHIPLET BASED STORAGE ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 18/641141 [patent_app_country] => US [patent_app_date] => 2024-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15779 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18641141 [rel_patent_id] =>[rel_patent_doc_number] =>)