Search

Demetrios C. Kerveros

Examiner (ID: 7334, Phone: (571)272-3824 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2117, 2111, 2138, 2133, 2858
Total Applications
2023
Issued Applications
1687
Pending Applications
116
Abandoned Applications
233

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16047703 [patent_doc_number] => 10685730 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-06-16 [patent_title] => Circuit including efficient clocking for testing memory interface [patent_app_type] => utility [patent_app_number] => 15/926414 [patent_app_country] => US [patent_app_date] => 2018-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 7482 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15926414 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/926414
Circuit including efficient clocking for testing memory interface Mar 19, 2018 Issued
Array ( [id] => 13998123 [patent_doc_number] => 20190068219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => BIT-FLIPPING DECODER FOR G-LDPC CODES WITH SYNDROME-DECODING FOR COMPONENT CODES [patent_app_type] => utility [patent_app_number] => 15/917222 [patent_app_country] => US [patent_app_date] => 2018-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9271 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15917222 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/917222
Bit-flipping decoder for G-LDPC codes with syndrome-decoding for component codes Mar 8, 2018 Issued
Array ( [id] => 12891367 [patent_doc_number] => 20180188964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => MANAGED STORAGE UNIT SHUTDOWN IN A DISTRIBUTED STORAGE NETWORK [patent_app_type] => utility [patent_app_number] => 15/900525 [patent_app_country] => US [patent_app_date] => 2018-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10738 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15900525 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/900525
MANAGED STORAGE UNIT SHUTDOWN IN A DISTRIBUTED STORAGE NETWORK Feb 19, 2018 Abandoned
Array ( [id] => 13843775 [patent_doc_number] => 20190025372 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-24 [patent_title] => ERROR RATE METER INCLUDED IN A SEMICONDUCTOR DIE [patent_app_type] => utility [patent_app_number] => 15/895784 [patent_app_country] => US [patent_app_date] => 2018-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7142 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15895784 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/895784
Error rate meter included in a semiconductor die Feb 12, 2018 Issued
Array ( [id] => 14718293 [patent_doc_number] => 20190250210 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-15 [patent_title] => System Architecture Method and Apparatus for Adaptive Hardware Fault Detection with Hardware Metrics Subsystem [patent_app_type] => utility [patent_app_number] => 15/893485 [patent_app_country] => US [patent_app_date] => 2018-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6991 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15893485 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/893485
System architecture method and apparatus for adaptive hardware fault detection with hardware metrics subsystem Feb 8, 2018 Issued
Array ( [id] => 15317261 [patent_doc_number] => 10523352 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-31 [patent_title] => Forward error correction for incomplete blocks [patent_app_type] => utility [patent_app_number] => 15/890219 [patent_app_country] => US [patent_app_date] => 2018-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 14161 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15890219 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/890219
Forward error correction for incomplete blocks Feb 5, 2018 Issued
Array ( [id] => 15820301 [patent_doc_number] => 10635327 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-28 [patent_title] => Data availability during memory inaccessibility [patent_app_type] => utility [patent_app_number] => 15/885770 [patent_app_country] => US [patent_app_date] => 2018-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 14130 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15885770 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/885770
Data availability during memory inaccessibility Jan 30, 2018 Issued
Array ( [id] => 12800101 [patent_doc_number] => 20180158536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-07 [patent_title] => Periodically Updating a Log Likelihood Ratio (LLR) Table in a Flash Memory Controller [patent_app_type] => utility [patent_app_number] => 15/884133 [patent_app_country] => US [patent_app_date] => 2018-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11058 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15884133 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/884133
Periodically updating a log likelihood ratio (LLR) table in a flash memory controller Jan 29, 2018 Issued
Array ( [id] => 14796761 [patent_doc_number] => 10401379 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-03 [patent_title] => Sensor device provided with a circuit for detection of single or multiple events for generating corresponding interrupt signals [patent_app_type] => utility [patent_app_number] => 15/884019 [patent_app_country] => US [patent_app_date] => 2018-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5340 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15884019 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/884019
Sensor device provided with a circuit for detection of single or multiple events for generating corresponding interrupt signals Jan 29, 2018 Issued
Array ( [id] => 12778162 [patent_doc_number] => 20180151222 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-31 [patent_title] => SOFT INFORMATION MODULE [patent_app_type] => utility [patent_app_number] => 15/882937 [patent_app_country] => US [patent_app_date] => 2018-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9139 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15882937 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/882937
Soft information module Jan 28, 2018 Issued
Array ( [id] => 13740165 [patent_doc_number] => 20180374552 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-27 [patent_title] => MEMORY SYSTEM AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/881243 [patent_app_country] => US [patent_app_date] => 2018-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12034 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15881243 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/881243
MEMORY SYSTEM AND OPERATION METHOD THEREOF Jan 25, 2018 Abandoned
Array ( [id] => 15820703 [patent_doc_number] => 10635531 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-28 [patent_title] => Semiconductor memory device error correction circuit, semiconductor memory device including the same, and memory system including the same [patent_app_type] => utility [patent_app_number] => 15/870220 [patent_app_country] => US [patent_app_date] => 2018-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 28 [patent_no_of_words] => 9490 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15870220 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/870220
Semiconductor memory device error correction circuit, semiconductor memory device including the same, and memory system including the same Jan 11, 2018 Issued
Array ( [id] => 15047095 [patent_doc_number] => 20190334552 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-31 [patent_title] => ENCODING METHOD AND ENCODER [patent_app_type] => utility [patent_app_number] => 16/476051 [patent_app_country] => US [patent_app_date] => 2018-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12378 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16476051 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/476051
Encoding method and encoder Jan 4, 2018 Issued
Array ( [id] => 15489505 [patent_doc_number] => 10560121 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-11 [patent_title] => Transmission method, transmission apparatus, reception method and reception apparatus [patent_app_type] => utility [patent_app_number] => 15/821011 [patent_app_country] => US [patent_app_date] => 2017-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 75 [patent_figures_cnt] => 82 [patent_no_of_words] => 69958 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 533 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15821011 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/821011
Transmission method, transmission apparatus, reception method and reception apparatus Nov 21, 2017 Issued
Array ( [id] => 12242038 [patent_doc_number] => 20180074900 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-15 [patent_title] => 'FIRST RESPONDER PARITIES FOR STORAGE ARRAY' [patent_app_type] => utility [patent_app_number] => 15/819409 [patent_app_country] => US [patent_app_date] => 2017-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7656 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15819409 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/819409
First responder parities for storage array Nov 20, 2017 Issued
Array ( [id] => 15820715 [patent_doc_number] => 10635537 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-28 [patent_title] => Raid data loss prevention [patent_app_type] => utility [patent_app_number] => 15/811393 [patent_app_country] => US [patent_app_date] => 2017-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 6393 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15811393 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/811393
Raid data loss prevention Nov 12, 2017 Issued
Array ( [id] => 16067249 [patent_doc_number] => 10692584 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-23 [patent_title] => Built-in self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register [patent_app_type] => utility [patent_app_number] => 15/801444 [patent_app_country] => US [patent_app_date] => 2017-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3174 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15801444 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/801444
Built-in self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register Nov 1, 2017 Issued
Array ( [id] => 15822621 [patent_doc_number] => 10636504 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-28 [patent_title] => Read verify for improved soft bit information for non-volatile memories with residual resistance [patent_app_type] => utility [patent_app_number] => 15/798648 [patent_app_country] => US [patent_app_date] => 2017-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 29 [patent_no_of_words] => 19694 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15798648 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/798648
Read verify for improved soft bit information for non-volatile memories with residual resistance Oct 30, 2017 Issued
Array ( [id] => 15474839 [patent_doc_number] => 10553302 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-04 [patent_title] => Built-in self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register [patent_app_type] => utility [patent_app_number] => 15/798858 [patent_app_country] => US [patent_app_date] => 2017-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3174 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15798858 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/798858
Built-in self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register Oct 30, 2017 Issued
Array ( [id] => 16322916 [patent_doc_number] => 10782879 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-22 [patent_title] => Memory system for controlling nonvolatile memory [patent_app_type] => utility [patent_app_number] => 15/785860 [patent_app_country] => US [patent_app_date] => 2017-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 31 [patent_no_of_words] => 17144 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15785860 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/785860
Memory system for controlling nonvolatile memory Oct 16, 2017 Issued
Menu