Search

Demetrios C. Kerveros

Examiner (ID: 7334, Phone: (571)272-3824 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2117, 2111, 2138, 2133, 2858
Total Applications
2023
Issued Applications
1687
Pending Applications
116
Abandoned Applications
233

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15106405 [patent_doc_number] => 10474528 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-12 [patent_title] => Redundancy coding stripe based on coordinated internal address scheme across multiple devices [patent_app_type] => utility [patent_app_number] => 15/722666 [patent_app_country] => US [patent_app_date] => 2017-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 19308 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15722666 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/722666
Redundancy coding stripe based on coordinated internal address scheme across multiple devices Oct 1, 2017 Issued
Array ( [id] => 14460985 [patent_doc_number] => 10326472 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-18 [patent_title] => Low density parity check encoder having length of 64800 and code rate of 4/15, and low density parity check encoding method using the same [patent_app_type] => utility [patent_app_number] => 15/709191 [patent_app_country] => US [patent_app_date] => 2017-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6641 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 862 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15709191 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/709191
Low density parity check encoder having length of 64800 and code rate of 4/15, and low density parity check encoding method using the same Sep 18, 2017 Issued
Array ( [id] => 14051065 [patent_doc_number] => 20190081640 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-14 [patent_title] => FAULTY WORD LINE AND FAULTY BIT LINE INFORMATION IN ERROR CORRECTING CODING [patent_app_type] => utility [patent_app_number] => 15/699939 [patent_app_country] => US [patent_app_date] => 2017-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8255 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15699939 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/699939
FAULTY WORD LINE AND FAULTY BIT LINE INFORMATION IN ERROR CORRECTING CODING Sep 7, 2017 Abandoned
Array ( [id] => 14047441 [patent_doc_number] => 20190079827 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-14 [patent_title] => DETECTING SILENT DATA CORRUPTION FOR MASS STORAGE DEVICES [patent_app_type] => utility [patent_app_number] => 15/699950 [patent_app_country] => US [patent_app_date] => 2017-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8480 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15699950 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/699950
Detecting silent data corruption for mass storage devices Sep 7, 2017 Issued
Array ( [id] => 13614877 [patent_doc_number] => 20180358989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-13 [patent_title] => Non-volatile Storage Systems With Application-Aware Error-Correcting Codes [patent_app_type] => utility [patent_app_number] => 15/696787 [patent_app_country] => US [patent_app_date] => 2017-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14725 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15696787 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/696787
Non-volatile Storage Systems With Application-Aware Error-Correcting Codes Sep 5, 2017 Abandoned
Array ( [id] => 16463887 [patent_doc_number] => 10847244 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-24 [patent_title] => Storage device including repairable volatile memory and method of operating the same [patent_app_type] => utility [patent_app_number] => 15/695366 [patent_app_country] => US [patent_app_date] => 2017-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 10989 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15695366 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/695366
Storage device including repairable volatile memory and method of operating the same Sep 4, 2017 Issued
Array ( [id] => 13451231 [patent_doc_number] => 20180277158 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-27 [patent_title] => STORAGE DEVICE AND CONTROLLER [patent_app_type] => utility [patent_app_number] => 15/694971 [patent_app_country] => US [patent_app_date] => 2017-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9924 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15694971 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/694971
Storage device and controller Sep 3, 2017 Issued
Array ( [id] => 12781117 [patent_doc_number] => 20180152207 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-31 [patent_title] => MEMORY CONTROLLER, MEMORY SYSTEM, AND CONTROL METHOD [patent_app_type] => utility [patent_app_number] => 15/693585 [patent_app_country] => US [patent_app_date] => 2017-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14497 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15693585 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/693585
Memory controller, memory system, and control method Aug 31, 2017 Issued
Array ( [id] => 12128175 [patent_doc_number] => 20180011760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-11 [patent_title] => 'MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 15/694471 [patent_app_country] => US [patent_app_date] => 2017-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 17257 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15694471 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/694471
Memory system and method of controlling nonvolatile memory Aug 31, 2017 Issued
Array ( [id] => 13990225 [patent_doc_number] => 20190064270 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => COMBINATORIAL SERIAL AND PARALLEL TEST ACCESS PORT SELECTION IN A JTAG INTERFACE [patent_app_type] => utility [patent_app_number] => 15/688184 [patent_app_country] => US [patent_app_date] => 2017-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3608 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15688184 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/688184
Combinatorial serial and parallel test access port selection in a JTAG interface Aug 27, 2017 Issued
Array ( [id] => 13322171 [patent_doc_number] => 20180212623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-26 [patent_title] => CONTROLLER AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/687631 [patent_app_country] => US [patent_app_date] => 2017-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10919 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15687631 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/687631
CONTROLLER AND OPERATING METHOD THEREOF Aug 27, 2017 Abandoned
Array ( [id] => 15545121 [patent_doc_number] => 10572341 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-25 [patent_title] => Semiconductor devices [patent_app_type] => utility [patent_app_number] => 15/687681 [patent_app_country] => US [patent_app_date] => 2017-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10268 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15687681 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/687681
Semiconductor devices Aug 27, 2017 Issued
Array ( [id] => 15141027 [patent_doc_number] => 10484012 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-11-19 [patent_title] => Systems and methods for decoding quasi-cyclic (QC) low-density parity-check (LDPC) codes [patent_app_type] => utility [patent_app_number] => 15/688628 [patent_app_country] => US [patent_app_date] => 2017-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 9228 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15688628 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/688628
Systems and methods for decoding quasi-cyclic (QC) low-density parity-check (LDPC) codes Aug 27, 2017 Issued
Array ( [id] => 13992305 [patent_doc_number] => 20190065310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => SYSTEM AND METHOD TO UTILIZE LARGER BLOCK SIZES FOR LOGICAL DISK AND FURTHER DECOMPOSE INTO SMALLER PHYSICAL BLOCK SIZES FOR REDUNDANT ENCODING BY UTILIZING ERASURE CODING [patent_app_type] => utility [patent_app_number] => 15/686908 [patent_app_country] => US [patent_app_date] => 2017-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7211 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15686908 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/686908
System and method to utilize larger block sizes for logical disk and further decompose into smaller physical block sizes for redundant encoding by utilizing erasure coding Aug 24, 2017 Issued
Array ( [id] => 12866500 [patent_doc_number] => 20180180675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-28 [patent_title] => SCAN DATA CONTROL APPARATUS AND ELECTRONIC SYSTEM HAVING THE SAME [patent_app_type] => utility [patent_app_number] => 15/680109 [patent_app_country] => US [patent_app_date] => 2017-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6593 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15680109 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/680109
Scan data control apparatus and electronic system having the same Aug 16, 2017 Issued
Array ( [id] => 13710461 [patent_doc_number] => 20170366185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-21 [patent_title] => INTEGRATED CIRCUIT (IC) CHIP COMPRISING AN IDENTIFICATION CIRCUIT [patent_app_type] => utility [patent_app_number] => 15/675705 [patent_app_country] => US [patent_app_date] => 2017-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7634 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15675705 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/675705
Integrated circuit (IC) chip comprising an identification circuit Aug 11, 2017 Issued
Array ( [id] => 14298719 [patent_doc_number] => 10289486 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-14 [patent_title] => Memory with pattern oriented error correction code [patent_app_type] => utility [patent_app_number] => 15/649451 [patent_app_country] => US [patent_app_date] => 2017-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5868 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15649451 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/649451
Memory with pattern oriented error correction code Jul 12, 2017 Issued
Array ( [id] => 14856733 [patent_doc_number] => 10417094 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-09-17 [patent_title] => Hyper storage cluster [patent_app_type] => utility [patent_app_number] => 15/649536 [patent_app_country] => US [patent_app_date] => 2017-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 16264 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15649536 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/649536
Hyper storage cluster Jul 12, 2017 Issued
Array ( [id] => 14298725 [patent_doc_number] => 10289489 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-14 [patent_title] => Update efficient consensus protocols for erasure coded data stores [patent_app_type] => utility [patent_app_number] => 15/647182 [patent_app_country] => US [patent_app_date] => 2017-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6195 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15647182 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/647182
Update efficient consensus protocols for erasure coded data stores Jul 10, 2017 Issued
Array ( [id] => 15477095 [patent_doc_number] => 10554444 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-04 [patent_title] => Method and device for operating a bus system [patent_app_type] => utility [patent_app_number] => 15/643791 [patent_app_country] => US [patent_app_date] => 2017-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4187 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15643791 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/643791
Method and device for operating a bus system Jul 6, 2017 Issued
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