Search

Denise J. Buckley

Examiner (ID: 5164)

Most Active Art Unit
3641
Art Unit(s)
3641
Total Applications
340
Issued Applications
302
Pending Applications
17
Abandoned Applications
21

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19484117 [patent_doc_number] => 20240332159 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/733459 [patent_app_country] => US [patent_app_date] => 2024-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10561 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18733459 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/733459
SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF Jun 3, 2024 Pending
Array ( [id] => 19484117 [patent_doc_number] => 20240332159 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/733459 [patent_app_country] => US [patent_app_date] => 2024-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10561 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18733459 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/733459
SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF Jun 3, 2024 Pending
Array ( [id] => 20307240 [patent_doc_number] => 12453251 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-21 [patent_title] => Display apparatus [patent_app_type] => utility [patent_app_number] => 18/665649 [patent_app_country] => US [patent_app_date] => 2024-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9374 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18665649 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/665649
Display apparatus May 15, 2024 Issued
Array ( [id] => 19392906 [patent_doc_number] => 20240282776 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => SEMICONDUCTOR STRUCTURE INCLUDING SECTIONED WELL REGION [patent_app_type] => utility [patent_app_number] => 18/653473 [patent_app_country] => US [patent_app_date] => 2024-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5239 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18653473 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/653473
SEMICONDUCTOR STRUCTURE INCLUDING SECTIONED WELL REGION May 1, 2024 Pending
Array ( [id] => 19364383 [patent_doc_number] => 20240266417 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => NEGATIVE CAPACITANCE TRANSISTOR WITH EXTERNAL FERROELECTRIC STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/635461 [patent_app_country] => US [patent_app_date] => 2024-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7869 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18635461 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/635461
NEGATIVE CAPACITANCE TRANSISTOR WITH EXTERNAL FERROELECTRIC STRUCTURE Apr 14, 2024 Pending
Array ( [id] => 20268645 [patent_doc_number] => 12439657 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Confined source/drain epitaxy regions and method forming same [patent_app_type] => utility [patent_app_number] => 18/589160 [patent_app_country] => US [patent_app_date] => 2024-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 2167 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18589160 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/589160
Confined source/drain epitaxy regions and method forming same Feb 26, 2024 Issued
Array ( [id] => 20268645 [patent_doc_number] => 12439657 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Confined source/drain epitaxy regions and method forming same [patent_app_type] => utility [patent_app_number] => 18/589160 [patent_app_country] => US [patent_app_date] => 2024-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 2167 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18589160 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/589160
Confined source/drain epitaxy regions and method forming same Feb 26, 2024 Issued
Array ( [id] => 20418465 [patent_doc_number] => 12501771 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-16 [patent_title] => Display device and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 18/418174 [patent_app_country] => US [patent_app_date] => 2024-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 9331 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18418174 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/418174
Display device and method of manufacturing the same Jan 18, 2024 Issued
Array ( [id] => 19161116 [patent_doc_number] => 20240153823 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => Gate Structures in Semiconductor Devices [patent_app_type] => utility [patent_app_number] => 18/416073 [patent_app_country] => US [patent_app_date] => 2024-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10035 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18416073 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/416073
Gate Structures in Semiconductor Devices Jan 17, 2024 Issued
Array ( [id] => 19161116 [patent_doc_number] => 20240153823 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => Gate Structures in Semiconductor Devices [patent_app_type] => utility [patent_app_number] => 18/416073 [patent_app_country] => US [patent_app_date] => 2024-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10035 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18416073 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/416073
Gate Structures in Semiconductor Devices Jan 17, 2024 Issued
Array ( [id] => 19161116 [patent_doc_number] => 20240153823 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => Gate Structures in Semiconductor Devices [patent_app_type] => utility [patent_app_number] => 18/416073 [patent_app_country] => US [patent_app_date] => 2024-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10035 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18416073 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/416073
Gate Structures in Semiconductor Devices Jan 17, 2024 Issued
Array ( [id] => 19509496 [patent_doc_number] => 12120938 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-10-15 [patent_title] => Methods of fabricating OLED panel with inorganic pixel encapsulating barrier [patent_app_type] => utility [patent_app_number] => 18/390720 [patent_app_country] => US [patent_app_date] => 2023-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 43 [patent_no_of_words] => 9456 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18390720 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/390720
Methods of fabricating OLED panel with inorganic pixel encapsulating barrier Dec 19, 2023 Issued
Array ( [id] => 19919819 [patent_doc_number] => 12295215 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-06 [patent_title] => Methods of fabricating OLED panel with inorganic pixel encapsulating barrier [patent_app_type] => utility [patent_app_number] => 18/545676 [patent_app_country] => US [patent_app_date] => 2023-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 43 [patent_no_of_words] => 4272 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18545676 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/545676
Methods of fabricating OLED panel with inorganic pixel encapsulating barrier Dec 18, 2023 Issued
Array ( [id] => 19071410 [patent_doc_number] => 20240105836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/537822 [patent_app_country] => US [patent_app_date] => 2023-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10014 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18537822 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/537822
SEMICONDUCTOR DEVICE Dec 12, 2023 Pending
Array ( [id] => 19071410 [patent_doc_number] => 20240105836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/537822 [patent_app_country] => US [patent_app_date] => 2023-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10014 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18537822 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/537822
SEMICONDUCTOR DEVICE Dec 12, 2023 Pending
Array ( [id] => 19086450 [patent_doc_number] => 20240113251 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => Device Including a Semiconductor Layer With Graded Composition [patent_app_type] => utility [patent_app_number] => 18/519778 [patent_app_country] => US [patent_app_date] => 2023-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15763 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18519778 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/519778
Device Including a Semiconductor Layer With Graded Composition Nov 26, 2023 Pending
Array ( [id] => 19628793 [patent_doc_number] => 12167669 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-10 [patent_title] => Display device and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 18/518622 [patent_app_country] => US [patent_app_date] => 2023-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 7745 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18518622 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/518622
Display device and method of manufacturing the same Nov 23, 2023 Issued
Array ( [id] => 20030863 [patent_doc_number] => 20250169085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-22 [patent_title] => SEMICONDUCTOR DEVICES INCLUDING CIRCUITS UNDER INDUCTOR (CUL) [patent_app_type] => utility [patent_app_number] => 18/513873 [patent_app_country] => US [patent_app_date] => 2023-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1117 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18513873 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/513873
SEMICONDUCTOR DEVICES INCLUDING CIRCUITS UNDER INDUCTOR (CUL) Nov 19, 2023 Pending
Array ( [id] => 20030863 [patent_doc_number] => 20250169085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-22 [patent_title] => SEMICONDUCTOR DEVICES INCLUDING CIRCUITS UNDER INDUCTOR (CUL) [patent_app_type] => utility [patent_app_number] => 18/513873 [patent_app_country] => US [patent_app_date] => 2023-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1117 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18513873 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/513873
SEMICONDUCTOR DEVICES INCLUDING CIRCUITS UNDER INDUCTOR (CUL) Nov 19, 2023 Pending
Array ( [id] => 19237578 [patent_doc_number] => 20240194773 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/495128 [patent_app_country] => US [patent_app_date] => 2023-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5366 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18495128 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/495128
HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD FOR FABRICATING THE SAME Oct 25, 2023 Pending
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