Search

Denise Tran

Examiner (ID: 13040, Phone: (571)272-4189 , Office: P/2138 )

Most Active Art Unit
2138
Art Unit(s)
2138, 2185, 2318, 2189, 2752, 2312, 2186, 2188, 2302
Total Applications
671
Issued Applications
551
Pending Applications
19
Abandoned Applications
103

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14542107 [patent_doc_number] => 20190206675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => MANUFACTURE OF GROUP IIIA-NITRIDE LAYERS ON SEMICONDUCTOR ON INSULATOR STRUCTURES [patent_app_type] => utility [patent_app_number] => 16/292441 [patent_app_country] => US [patent_app_date] => 2019-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10616 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16292441 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/292441
Manufacture of group IIIA-nitride layers on semiconductor on insulator structures Mar 4, 2019 Issued
Array ( [id] => 16660584 [patent_doc_number] => 20210057221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-25 [patent_title] => METHOD FOR PREPARING OHMIC CONTACT ELECTRODE OF GALLIUM NITRIDE-BASED DEVICE [patent_app_type] => utility [patent_app_number] => 16/968977 [patent_app_country] => US [patent_app_date] => 2019-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2491 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16968977 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/968977
Method for preparing ohmic contact electrode of gallium nitride-based device Feb 26, 2019 Issued
Array ( [id] => 16364767 [patent_doc_number] => 20200321518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-08 [patent_title] => FERROMAGNETIC LAMINATED FILM, SPIN CURRENT MAGNETIZATION ROTATING ELEMENT, MAGNETORESISTANCE EFFECT ELEMENT, AND MAGNETIC MEMORY [patent_app_type] => utility [patent_app_number] => 16/956802 [patent_app_country] => US [patent_app_date] => 2019-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10372 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16956802 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/956802
Ferromagnetic laminated film, spin current magnetization rotating element, magnetoresistance effect element, and magnetic memory Feb 25, 2019 Issued
Array ( [id] => 17011127 [patent_doc_number] => 20210242288 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-05 [patent_title] => ARRAY SUBSTRATE AND FLEXIBLE DISPLAY PANEL [patent_app_type] => utility [patent_app_number] => 16/467048 [patent_app_country] => US [patent_app_date] => 2019-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3425 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16467048 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/467048
Array substrate and flexible display panel Feb 20, 2019 Issued
Array ( [id] => 17544264 [patent_doc_number] => 11309399 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-19 [patent_title] => Process for preparing a thin layer of ferroelectric material [patent_app_type] => utility [patent_app_number] => 16/980310 [patent_app_country] => US [patent_app_date] => 2019-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 4103 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16980310 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/980310
Process for preparing a thin layer of ferroelectric material Feb 17, 2019 Issued
Array ( [id] => 15123505 [patent_doc_number] => 20190348386 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-14 [patent_title] => CHIP PACKAGE STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/277806 [patent_app_country] => US [patent_app_date] => 2019-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7314 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16277806 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/277806
Chip package structure Feb 14, 2019 Issued
Array ( [id] => 16521631 [patent_doc_number] => 10872856 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-22 [patent_title] => Semiconductor device including through vias in molded columns [patent_app_type] => utility [patent_app_number] => 16/277467 [patent_app_country] => US [patent_app_date] => 2019-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 4381 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16277467 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/277467
Semiconductor device including through vias in molded columns Feb 14, 2019 Issued
Array ( [id] => 16256758 [patent_doc_number] => 20200266133 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-20 [patent_title] => SEMICONDUCTOR PACKAGE WITH LEADFRAME HAVING PRE-SINGULATED LEADS OR LEAD TERMINALS [patent_app_type] => utility [patent_app_number] => 16/277462 [patent_app_country] => US [patent_app_date] => 2019-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3314 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16277462 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/277462
Semiconductor package with leadframe having pre-singulated leads or lead terminals Feb 14, 2019 Issued
Array ( [id] => 16256851 [patent_doc_number] => 20200266226 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-20 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 16/277585 [patent_app_country] => US [patent_app_date] => 2019-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4207 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16277585 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/277585
Semiconductor device and method for forming the same Feb 14, 2019 Issued
Array ( [id] => 14754013 [patent_doc_number] => 20190260180 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-22 [patent_title] => LIGHT-EMITTING CHIP PACKAGE [patent_app_type] => utility [patent_app_number] => 16/277784 [patent_app_country] => US [patent_app_date] => 2019-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7940 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16277784 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/277784
Light-emitting chip package Feb 14, 2019 Issued
Array ( [id] => 16148257 [patent_doc_number] => 10707207 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-07-07 [patent_title] => Method, apparatus, and system for improved gate connections on isolation structures in FinFET devices [patent_app_type] => utility [patent_app_number] => 16/277496 [patent_app_country] => US [patent_app_date] => 2019-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 6772 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 565 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16277496 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/277496
Method, apparatus, and system for improved gate connections on isolation structures in FinFET devices Feb 14, 2019 Issued
Array ( [id] => 15442981 [patent_doc_number] => 20200035674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-30 [patent_title] => GATE CUT LAST PROCESSING WITH SELF-ALIGNED SPACER [patent_app_type] => utility [patent_app_number] => 16/277751 [patent_app_country] => US [patent_app_date] => 2019-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7339 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16277751 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/277751
GATE CUT LAST PROCESSING WITH SELF-ALIGNED SPACER Feb 14, 2019 Abandoned
Array ( [id] => 15503447 [patent_doc_number] => 20200051912 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING RESISTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/277597 [patent_app_country] => US [patent_app_date] => 2019-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9602 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16277597 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/277597
Semiconductor device including resistor structure Feb 14, 2019 Issued
Array ( [id] => 15597809 [patent_doc_number] => 20200075439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-05 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/277566 [patent_app_country] => US [patent_app_date] => 2019-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5361 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16277566 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/277566
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE Feb 14, 2019 Abandoned
Array ( [id] => 16631597 [patent_doc_number] => 20210050250 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-18 [patent_title] => METHOD FOR MANUFACTURING A SEMICONDUCTOR ON INSULATOR TYPE STRUCTURE BY LAYER TRANSFER [patent_app_type] => utility [patent_app_number] => 16/969350 [patent_app_country] => US [patent_app_date] => 2019-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6230 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16969350 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/969350
Method for manufacturing a semiconductor on insulator type structure by layer transfer Feb 11, 2019 Issued
Array ( [id] => 16187159 [patent_doc_number] => 10720500 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-21 [patent_title] => Transistor device with a field electrode that includes two layers [patent_app_type] => utility [patent_app_number] => 16/270806 [patent_app_country] => US [patent_app_date] => 2019-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 5319 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16270806 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/270806
Transistor device with a field electrode that includes two layers Feb 7, 2019 Issued
Array ( [id] => 17181509 [patent_doc_number] => 11158760 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-26 [patent_title] => Metal organic chemical vapor depostion (MOCVD) tunnel junction growth in III-nitride devices [patent_app_type] => utility [patent_app_number] => 16/270177 [patent_app_country] => US [patent_app_date] => 2019-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 24 [patent_no_of_words] => 6793 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16270177 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/270177
Metal organic chemical vapor depostion (MOCVD) tunnel junction growth in III-nitride devices Feb 6, 2019 Issued
Array ( [id] => 14722697 [patent_doc_number] => 20190252412 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-15 [patent_title] => DISPLAY INCLUDING PLURALITY OF WIRING LAYERS IN BENDING REGION [patent_app_type] => utility [patent_app_number] => 16/269981 [patent_app_country] => US [patent_app_date] => 2019-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15618 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16269981 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/269981
Display including plurality of wiring layers in bending region Feb 6, 2019 Issued
Array ( [id] => 16241552 [patent_doc_number] => 20200258786 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-13 [patent_title] => MUTLIPLE DIELECTRICS FOR GATE-ALL-AROUND TRANSISTORS [patent_app_type] => utility [patent_app_number] => 16/270174 [patent_app_country] => US [patent_app_date] => 2019-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6699 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16270174 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/270174
Multiple dielectrics for gate-all-around transistors Feb 6, 2019 Issued
Array ( [id] => 16226503 [patent_doc_number] => 20200251620 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-06 [patent_title] => Two Component Glass Body for Tape Casting Phosphor in Glass LED Converters [patent_app_type] => utility [patent_app_number] => 16/269396 [patent_app_country] => US [patent_app_date] => 2019-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5361 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16269396 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/269396
Two component glass body for tape casting phosphor in glass LED converters Feb 5, 2019 Issued
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