Search

Denise Tran

Examiner (ID: 9375, Phone: (571)272-4189 , Office: P/2138 )

Most Active Art Unit
2138
Art Unit(s)
2318, 2312, 2138, 2189, 2188, 2185, 2752, 2186, 2302
Total Applications
671
Issued Applications
551
Pending Applications
19
Abandoned Applications
103

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6881001 [patent_doc_number] => 20010032289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-18 [patent_title] => 'Memory writing device for an electronic device' [patent_app_type] => new [patent_app_number] => 09/843821 [patent_app_country] => US [patent_app_date] => 2001-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 15368 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20010032289.pdf [firstpage_image] =>[orig_patent_app_number] => 09843821 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/843821
Memory writing device for an electronic device Apr 29, 2001 Issued
Array ( [id] => 6962806 [patent_doc_number] => 20010013085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-09 [patent_title] => 'Storage control apparatus' [patent_app_type] => new [patent_app_number] => 09/804186 [patent_app_country] => US [patent_app_date] => 2001-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7945 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20010013085.pdf [firstpage_image] =>[orig_patent_app_number] => 09804186 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/804186
Storage control apparatus Mar 12, 2001 Abandoned
Array ( [id] => 7095082 [patent_doc_number] => 20010034822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-25 [patent_title] => 'Method and apparatus for virtual memory mapping and transaction management in an object-oriented database system' [patent_app_type] => new [patent_app_number] => 09/800257 [patent_app_country] => US [patent_app_date] => 2001-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 15107 [patent_no_of_claims] => 117 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20010034822.pdf [firstpage_image] =>[orig_patent_app_number] => 09800257 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/800257
Method and apparatus for virtual memory mapping and transaction management in an object-oriented database system Mar 5, 2001 Issued
Array ( [id] => 6890774 [patent_doc_number] => 20010008005 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-07-12 [patent_title] => 'Method and apparatus for configuring and initializing a memory device and a memory channel' [patent_app_type] => new-utility [patent_app_number] => 09/779072 [patent_app_country] => US [patent_app_date] => 2001-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10074 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20010008005.pdf [firstpage_image] =>[orig_patent_app_number] => 09779072 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/779072
Method and apparatus for configuring and initializing a memory device and a memory channel Feb 6, 2001 Issued
Array ( [id] => 1509009 [patent_doc_number] => 06467022 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Extending adapter memory with solid state disks in JBOD and RAID environments' [patent_app_type] => B1 [patent_app_number] => 09/706111 [patent_app_country] => US [patent_app_date] => 2000-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4362 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/467/06467022.pdf [firstpage_image] =>[orig_patent_app_number] => 09706111 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/706111
Extending adapter memory with solid state disks in JBOD and RAID environments Nov 2, 2000 Issued
Array ( [id] => 1480991 [patent_doc_number] => 06389504 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Updating texture mapping hardware local memory based on pixel information provided by a host computer' [patent_app_type] => B1 [patent_app_number] => 09/661094 [patent_app_country] => US [patent_app_date] => 2000-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 33206 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/389/06389504.pdf [firstpage_image] =>[orig_patent_app_number] => 09661094 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/661094
Updating texture mapping hardware local memory based on pixel information provided by a host computer Sep 12, 2000 Issued
Array ( [id] => 1109749 [patent_doc_number] => 06813687 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-02 [patent_title] => 'Raid volume for sequential use that needs no redundancy pre-initialization' [patent_app_type] => B1 [patent_app_number] => 09/645949 [patent_app_country] => US [patent_app_date] => 2000-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2737 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/813/06813687.pdf [firstpage_image] =>[orig_patent_app_number] => 09645949 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/645949
Raid volume for sequential use that needs no redundancy pre-initialization Aug 24, 2000 Issued
Array ( [id] => 609449 [patent_doc_number] => 07155559 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-12-26 [patent_title] => 'Flash memory architecture with separate storage of overhead and user data' [patent_app_type] => utility [patent_app_number] => 09/648271 [patent_app_country] => US [patent_app_date] => 2000-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 24 [patent_no_of_words] => 17045 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/155/07155559.pdf [firstpage_image] =>[orig_patent_app_number] => 09648271 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/648271
Flash memory architecture with separate storage of overhead and user data Aug 24, 2000 Issued
Array ( [id] => 1161407 [patent_doc_number] => 06775740 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-10 [patent_title] => 'Processor having a selector circuit for selecting an output signal from a hit/miss judgement circuit and data from a register file' [patent_app_type] => B1 [patent_app_number] => 09/645406 [patent_app_country] => US [patent_app_date] => 2000-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 6259 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 317 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/775/06775740.pdf [firstpage_image] =>[orig_patent_app_number] => 09645406 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/645406
Processor having a selector circuit for selecting an output signal from a hit/miss judgement circuit and data from a register file Aug 24, 2000 Issued
Array ( [id] => 1033698 [patent_doc_number] => 06880046 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-04-12 [patent_title] => 'Multiprocessor system and memory access method' [patent_app_type] => utility [patent_app_number] => 09/645880 [patent_app_country] => US [patent_app_date] => 2000-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6239 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/880/06880046.pdf [firstpage_image] =>[orig_patent_app_number] => 09645880 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/645880
Multiprocessor system and memory access method Aug 24, 2000 Issued
Array ( [id] => 7629992 [patent_doc_number] => 06636947 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-21 [patent_title] => 'Coherency for DMA read cached data' [patent_app_type] => B1 [patent_app_number] => 09/645177 [patent_app_country] => US [patent_app_date] => 2000-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2091 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/636/06636947.pdf [firstpage_image] =>[orig_patent_app_number] => 09645177 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/645177
Coherency for DMA read cached data Aug 23, 2000 Issued
Array ( [id] => 7613845 [patent_doc_number] => 06898686 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-24 [patent_title] => 'Memory map adjustment to support the need of adapters with large memory requirements' [patent_app_type] => utility [patent_app_number] => 09/645175 [patent_app_country] => US [patent_app_date] => 2000-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3720 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/898/06898686.pdf [firstpage_image] =>[orig_patent_app_number] => 09645175 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/645175
Memory map adjustment to support the need of adapters with large memory requirements Aug 23, 2000 Issued
Array ( [id] => 1017184 [patent_doc_number] => 06895471 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-17 [patent_title] => 'Method and apparatus for synchronizing cache with target tables in a data warehousing system' [patent_app_type] => utility [patent_app_number] => 09/644280 [patent_app_country] => US [patent_app_date] => 2000-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6759 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/895/06895471.pdf [firstpage_image] =>[orig_patent_app_number] => 09644280 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/644280
Method and apparatus for synchronizing cache with target tables in a data warehousing system Aug 21, 2000 Issued
Array ( [id] => 1097307 [patent_doc_number] => 06826650 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-30 [patent_title] => 'Disk controller configured to perform out of order execution of write operations' [patent_app_type] => B1 [patent_app_number] => 09/643636 [patent_app_country] => US [patent_app_date] => 2000-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8700 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/826/06826650.pdf [firstpage_image] =>[orig_patent_app_number] => 09643636 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/643636
Disk controller configured to perform out of order execution of write operations Aug 21, 2000 Issued
Array ( [id] => 645518 [patent_doc_number] => 07124252 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-10-17 [patent_title] => 'Method and apparatus for pipelining ordered input/output transactions to coherent memory in a distributed memory, cache coherent, multi-processor system' [patent_app_type] => utility [patent_app_number] => 09/643380 [patent_app_country] => US [patent_app_date] => 2000-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4985 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/124/07124252.pdf [firstpage_image] =>[orig_patent_app_number] => 09643380 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/643380
Method and apparatus for pipelining ordered input/output transactions to coherent memory in a distributed memory, cache coherent, multi-processor system Aug 20, 2000 Issued
Array ( [id] => 1055785 [patent_doc_number] => 06859855 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-22 [patent_title] => 'Data processing device' [patent_app_type] => utility [patent_app_number] => 09/642433 [patent_app_country] => US [patent_app_date] => 2000-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4585 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/859/06859855.pdf [firstpage_image] =>[orig_patent_app_number] => 09642433 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/642433
Data processing device Aug 20, 2000 Issued
Array ( [id] => 1129568 [patent_doc_number] => 06795890 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-21 [patent_title] => 'Data storage method, and data processing device using an erasure block buffer and write buffer for writing and erasing data in memory' [patent_app_type] => B1 [patent_app_number] => 09/640454 [patent_app_country] => US [patent_app_date] => 2000-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 53 [patent_figures_cnt] => 57 [patent_no_of_words] => 43297 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/795/06795890.pdf [firstpage_image] =>[orig_patent_app_number] => 09640454 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/640454
Data storage method, and data processing device using an erasure block buffer and write buffer for writing and erasing data in memory Aug 16, 2000 Issued
Array ( [id] => 937499 [patent_doc_number] => 06976118 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-12-13 [patent_title] => 'Method and system for programming FPGAs on PC-cards without additional hardware' [patent_app_type] => utility [patent_app_number] => 09/637214 [patent_app_country] => US [patent_app_date] => 2000-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2132 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/976/06976118.pdf [firstpage_image] =>[orig_patent_app_number] => 09637214 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/637214
Method and system for programming FPGAs on PC-cards without additional hardware Aug 10, 2000 Issued
Array ( [id] => 1567299 [patent_doc_number] => 06438645 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Apparatus and structure for rapid enablement' [patent_app_type] => B1 [patent_app_number] => 09/629602 [patent_app_country] => US [patent_app_date] => 2000-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2608 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/438/06438645.pdf [firstpage_image] =>[orig_patent_app_number] => 09629602 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/629602
Apparatus and structure for rapid enablement Jul 30, 2000 Issued
Array ( [id] => 7645897 [patent_doc_number] => 06477626 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-05 [patent_title] => 'Memory writing device for an electronic device' [patent_app_type] => B1 [patent_app_number] => 09/625403 [patent_app_country] => US [patent_app_date] => 2000-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 15217 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/477/06477626.pdf [firstpage_image] =>[orig_patent_app_number] => 09625403 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/625403
Memory writing device for an electronic device Jul 24, 2000 Issued
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