Search

Denise Tran

Examiner (ID: 9375, Phone: (571)272-4189 , Office: P/2138 )

Most Active Art Unit
2138
Art Unit(s)
2318, 2312, 2138, 2189, 2188, 2185, 2752, 2186, 2302
Total Applications
671
Issued Applications
551
Pending Applications
19
Abandoned Applications
103

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4337161 [patent_doc_number] => 06249848 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Memory writing device for an electronic device' [patent_app_type] => 1 [patent_app_number] => 9/625402 [patent_app_country] => US [patent_app_date] => 2000-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 14759 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/249/06249848.pdf [firstpage_image] =>[orig_patent_app_number] => 625402 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/625402
Memory writing device for an electronic device Jul 24, 2000 Issued
Array ( [id] => 1438697 [patent_doc_number] => 06356992 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Method and apparatus for interleaved exchange in a network mesh' [patent_app_type] => B1 [patent_app_number] => 09/624287 [patent_app_country] => US [patent_app_date] => 2000-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 27 [patent_no_of_words] => 2557 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/356/06356992.pdf [firstpage_image] =>[orig_patent_app_number] => 09624287 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/624287
Method and apparatus for interleaved exchange in a network mesh Jul 23, 2000 Issued
09/611616 Content addressable memory structures Jul 6, 2000 Abandoned
Array ( [id] => 524668 [patent_doc_number] => 07197623 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-03-27 [patent_title] => 'Multiple processor cellular radio' [patent_app_type] => utility [patent_app_number] => 09/606057 [patent_app_country] => US [patent_app_date] => 2000-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 3660 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/197/07197623.pdf [firstpage_image] =>[orig_patent_app_number] => 09606057 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/606057
Multiple processor cellular radio Jun 27, 2000 Issued
Array ( [id] => 7644128 [patent_doc_number] => 06473846 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'Content addressable memory (CAM) engine' [patent_app_type] => B1 [patent_app_number] => 09/596165 [patent_app_country] => US [patent_app_date] => 2000-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 13382 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/473/06473846.pdf [firstpage_image] =>[orig_patent_app_number] => 09596165 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/596165
Content addressable memory (CAM) engine Jun 15, 2000 Issued
09/581186 MEMORY ADDRESSING Jun 14, 2000 Abandoned
Array ( [id] => 4280741 [patent_doc_number] => 06260110 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Virtual tape system with variable size' [patent_app_type] => 1 [patent_app_number] => 9/578121 [patent_app_country] => US [patent_app_date] => 2000-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7062 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/260/06260110.pdf [firstpage_image] =>[orig_patent_app_number] => 578121 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/578121
Virtual tape system with variable size May 23, 2000 Issued
Array ( [id] => 268538 [patent_doc_number] => 07568067 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-07-28 [patent_title] => 'Method for controlling magnetic tape unit' [patent_app_type] => utility [patent_app_number] => 09/539805 [patent_app_country] => US [patent_app_date] => 2000-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 215 [patent_figures_cnt] => 446 [patent_no_of_words] => 103354 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/568/07568067.pdf [firstpage_image] =>[orig_patent_app_number] => 09539805 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/539805
Method for controlling magnetic tape unit Mar 29, 2000 Issued
Array ( [id] => 1100391 [patent_doc_number] => 06823434 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-23 [patent_title] => 'System and method for resetting and initializing a fully associative array to a known state at power on or through machine specific state' [patent_app_type] => B1 [patent_app_number] => 09/510128 [patent_app_country] => US [patent_app_date] => 2000-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3477 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/823/06823434.pdf [firstpage_image] =>[orig_patent_app_number] => 09510128 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/510128
System and method for resetting and initializing a fully associative array to a known state at power on or through machine specific state Feb 20, 2000 Issued
Array ( [id] => 1161532 [patent_doc_number] => 06775752 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-10 [patent_title] => 'System and method for efficiently updating a fully associative array' [patent_app_type] => B1 [patent_app_number] => 09/510288 [patent_app_country] => US [patent_app_date] => 2000-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 8008 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/775/06775752.pdf [firstpage_image] =>[orig_patent_app_number] => 09510288 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/510288
System and method for efficiently updating a fully associative array Feb 20, 2000 Issued
Array ( [id] => 1279434 [patent_doc_number] => 06654849 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-25 [patent_title] => 'Method and apparatus to minimize additional address bits and loading when adding a small patch RAM to a microcode ROM' [patent_app_type] => B1 [patent_app_number] => 09/507035 [patent_app_country] => US [patent_app_date] => 2000-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1754 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/654/06654849.pdf [firstpage_image] =>[orig_patent_app_number] => 09507035 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/507035
Method and apparatus to minimize additional address bits and loading when adding a small patch RAM to a microcode ROM Feb 17, 2000 Issued
Array ( [id] => 744949 [patent_doc_number] => 07035989 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-04-25 [patent_title] => 'Adaptive memory allocation' [patent_app_type] => utility [patent_app_number] => 09/504876 [patent_app_country] => US [patent_app_date] => 2000-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2543 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/035/07035989.pdf [firstpage_image] =>[orig_patent_app_number] => 09504876 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/504876
Adaptive memory allocation Feb 15, 2000 Issued
Array ( [id] => 1434039 [patent_doc_number] => 06341329 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-22 [patent_title] => 'Virtual tape system' [patent_app_type] => B1 [patent_app_number] => 09/501509 [patent_app_country] => US [patent_app_date] => 2000-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6392 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/341/06341329.pdf [firstpage_image] =>[orig_patent_app_number] => 09501509 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/501509
Virtual tape system Feb 8, 2000 Issued
Array ( [id] => 1604473 [patent_doc_number] => 06434659 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'MICROCOMPUTER HAVING A NON-VOLATILE SEMICONDUCTOR MEMORY HAVING A FIRST BLOCK STORING A PROGRAM AND A SECOND BLOCK FOR STORING DATA WHICH IS SELECTIVELY ERASED UNDER PREDETERMINED CONDITIONS IF DATA IS FOUND WRITTEN IN THAT BLOCK' [patent_app_type] => B1 [patent_app_number] => 09/480155 [patent_app_country] => US [patent_app_date] => 2000-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 6770 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434659.pdf [firstpage_image] =>[orig_patent_app_number] => 09480155 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/480155
MICROCOMPUTER HAVING A NON-VOLATILE SEMICONDUCTOR MEMORY HAVING A FIRST BLOCK STORING A PROGRAM AND A SECOND BLOCK FOR STORING DATA WHICH IS SELECTIVELY ERASED UNDER PREDETERMINED CONDITIONS IF DATA IS FOUND WRITTEN IN THAT BLOCK Jan 9, 2000 Issued
Array ( [id] => 4373747 [patent_doc_number] => 06202132 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Flexible cache-coherency mechanism' [patent_app_type] => 1 [patent_app_number] => 9/473660 [patent_app_country] => US [patent_app_date] => 1999-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 1156 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/202/06202132.pdf [firstpage_image] =>[orig_patent_app_number] => 473660 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/473660
Flexible cache-coherency mechanism Dec 28, 1999 Issued
Array ( [id] => 279838 [patent_doc_number] => 07558923 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-07-07 [patent_title] => 'Prevention of live-lock in a multi-processor system' [patent_app_type] => utility [patent_app_number] => 09/470329 [patent_app_country] => US [patent_app_date] => 1999-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3599 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/558/07558923.pdf [firstpage_image] =>[orig_patent_app_number] => 09470329 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/470329
Prevention of live-lock in a multi-processor system Dec 21, 1999 Issued
09/466335 METHOD AND APPARATUS FOR MONITORING A CACHE FOR GARBAGE COLLECTION Dec 16, 1999 Abandoned
Array ( [id] => 1311397 [patent_doc_number] => 06625714 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-23 [patent_title] => 'Parallel distributed function translation lookaside buffer' [patent_app_type] => B1 [patent_app_number] => 09/466494 [patent_app_country] => US [patent_app_date] => 1999-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4671 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/625/06625714.pdf [firstpage_image] =>[orig_patent_app_number] => 09466494 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/466494
Parallel distributed function translation lookaside buffer Dec 16, 1999 Issued
Array ( [id] => 1580378 [patent_doc_number] => 06470437 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-22 [patent_title] => 'Updating and invalidating store data and removing stale cache lines in a prevalidated tag cache design' [patent_app_type] => B1 [patent_app_number] => 09/466306 [patent_app_country] => US [patent_app_date] => 1999-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6717 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/470/06470437.pdf [firstpage_image] =>[orig_patent_app_number] => 09466306 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/466306
Updating and invalidating store data and removing stale cache lines in a prevalidated tag cache design Dec 16, 1999 Issued
Array ( [id] => 1521694 [patent_doc_number] => 06502163 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-31 [patent_title] => 'Method and apparatus for ordering entries in a ternary content addressable memory' [patent_app_type] => B1 [patent_app_number] => 09/465638 [patent_app_country] => US [patent_app_date] => 1999-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 7344 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/502/06502163.pdf [firstpage_image] =>[orig_patent_app_number] => 09465638 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/465638
Method and apparatus for ordering entries in a ternary content addressable memory Dec 16, 1999 Issued
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