
Denise Tran
Examiner (ID: 10341, Phone: (571)272-4189 , Office: P/2138 )
| Most Active Art Unit | 2138 |
| Art Unit(s) | 2302, 2185, 2312, 2138, 2186, 2318, 2189, 2188, 2752 |
| Total Applications | 671 |
| Issued Applications | 551 |
| Pending Applications | 19 |
| Abandoned Applications | 103 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 15027293
[patent_doc_number] => 20190324651
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-10-24
[patent_title] => POOL PARTNER BASED REPLICATION
[patent_app_type] => utility
[patent_app_number] => 15/960226
[patent_app_country] => US
[patent_app_date] => 2018-04-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6411
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 176
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15960226
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/960226 | Pool partner based replication | Apr 22, 2018 | Issued |
Array
(
[id] => 15671205
[patent_doc_number] => 10599835
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-03-24
[patent_title] => 32-bit address space containment to secure processes from speculative rogue cache loads
[patent_app_type] => utility
[patent_app_number] => 15/960467
[patent_app_country] => US
[patent_app_date] => 2018-04-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 7034
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 176
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15960467
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/960467 | 32-bit address space containment to secure processes from speculative rogue cache loads | Apr 22, 2018 | Issued |
Array
(
[id] => 16291967
[patent_doc_number] => 10768816
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-09-08
[patent_title] => Method and apparatus to manipulate customer data without using the host interface
[patent_app_type] => utility
[patent_app_number] => 15/959875
[patent_app_country] => US
[patent_app_date] => 2018-04-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 5765
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15959875
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/959875 | Method and apparatus to manipulate customer data without using the host interface | Apr 22, 2018 | Issued |
Array
(
[id] => 15027363
[patent_doc_number] => 20190324686
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-10-24
[patent_title] => Access to DRAM Through a Reuse of Pins
[patent_app_type] => utility
[patent_app_number] => 15/959764
[patent_app_country] => US
[patent_app_date] => 2018-04-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8919
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15959764
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/959764 | Access to DRAM through a reuse of pins | Apr 22, 2018 | Issued |
Array
(
[id] => 14508871
[patent_doc_number] => 20190198090
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-06-27
[patent_title] => SYSTEMS AND METHODS FOR PERFORMING ROW HAMMER REFRESH OPERATIONS IN REDUNDANT MEMORY
[patent_app_type] => utility
[patent_app_number] => 15/855514
[patent_app_country] => US
[patent_app_date] => 2017-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11427
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15855514
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/855514 | Systems and methods for performing row hammer refresh operations in redundant memory | Dec 26, 2017 | Issued |
Array
(
[id] => 12868945
[patent_doc_number] => 20180181490
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-06-28
[patent_title] => SYSTEM AND METHOD FOR SELF-INVALIDATION, SELF-DOWNGRADE CACHECOHERENCE PROTOCOLS
[patent_app_type] => utility
[patent_app_number] => 15/855378
[patent_app_country] => US
[patent_app_date] => 2017-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4759
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 50
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15855378
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/855378 | System and method for self-invalidation, self-downgrade cachecoherence protocols | Dec 26, 2017 | Issued |
Array
(
[id] => 14506639
[patent_doc_number] => 20190196974
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-06-27
[patent_title] => TAG ACCELERATOR FOR LOW LATENCY DRAM CACHE
[patent_app_type] => utility
[patent_app_number] => 15/855838
[patent_app_country] => US
[patent_app_date] => 2017-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5769
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15855838
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/855838 | Tag accelerator for low latency DRAM cache | Dec 26, 2017 | Issued |
Array
(
[id] => 14011213
[patent_doc_number] => 10224081
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-03-05
[patent_title] => Dynamic random access memory (DRAM) backchannel communication systems and methods
[patent_app_type] => utility
[patent_app_number] => 15/849463
[patent_app_country] => US
[patent_app_date] => 2017-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 5681
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15849463
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/849463 | Dynamic random access memory (DRAM) backchannel communication systems and methods | Dec 19, 2017 | Issued |
Array
(
[id] => 15516213
[patent_doc_number] => 10564690
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-02-18
[patent_title] => Power interrupt management
[patent_app_type] => utility
[patent_app_number] => 15/840646
[patent_app_country] => US
[patent_app_date] => 2017-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 5800
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15840646
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/840646 | Power interrupt management | Dec 12, 2017 | Issued |
Array
(
[id] => 14735853
[patent_doc_number] => 10387326
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-08-20
[patent_title] => Incorporating purge history into least-recently-used states of a translation lookaside buffer
[patent_app_type] => utility
[patent_app_number] => 15/811807
[patent_app_country] => US
[patent_app_date] => 2017-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5879
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15811807
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/811807 | Incorporating purge history into least-recently-used states of a translation lookaside buffer | Nov 13, 2017 | Issued |
Array
(
[id] => 14265113
[patent_doc_number] => 10282120
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-05-07
[patent_title] => Method, apparatus and system for inserting disk
[patent_app_type] => utility
[patent_app_number] => 15/722850
[patent_app_country] => US
[patent_app_date] => 2017-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 9262
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 194
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15722850
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/722850 | Method, apparatus and system for inserting disk | Oct 1, 2017 | Issued |
Array
(
[id] => 14952437
[patent_doc_number] => 10437482
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-10-08
[patent_title] => Coordinated near-far memory controller for process-in-HBM
[patent_app_type] => utility
[patent_app_number] => 15/723014
[patent_app_country] => US
[patent_app_date] => 2017-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 6792
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15723014
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/723014 | Coordinated near-far memory controller for process-in-HBM | Oct 1, 2017 | Issued |
Array
(
[id] => 15982417
[patent_doc_number] => 10671536
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-06-02
[patent_title] => Method and apparatus for cache pre-fetch with offset directives
[patent_app_type] => utility
[patent_app_number] => 15/722986
[patent_app_country] => US
[patent_app_date] => 2017-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 5375
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15722986
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/722986 | Method and apparatus for cache pre-fetch with offset directives | Oct 1, 2017 | Issued |
Array
(
[id] => 12053319
[patent_doc_number] => 20170329663
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-11-16
[patent_title] => 'DETERMINING CAUSES OF EXTERNAL FRAGMENTATION OF MEMORY'
[patent_app_type] => utility
[patent_app_number] => 15/668733
[patent_app_country] => US
[patent_app_date] => 2017-08-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 6856
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15668733
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/668733 | Determining causes of external fragmentation of memory | Aug 3, 2017 | Issued |
Array
(
[id] => 12140257
[patent_doc_number] => 20180018340
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-01-18
[patent_title] => 'INFORMATION PROCESSING SYSTEM, INFORMATION PROCESSING APPARATUS, AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM'
[patent_app_type] => utility
[patent_app_number] => 15/624029
[patent_app_country] => US
[patent_app_date] => 2017-06-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 33
[patent_figures_cnt] => 33
[patent_no_of_words] => 18747
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15624029
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/624029 | Information processing system, information processing apparatus, and non-transitory computer-readable recording medium | Jun 14, 2017 | Issued |
Array
(
[id] => 14856409
[patent_doc_number] => 10416928
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-09-17
[patent_title] => Data storage system and process for data compression of distributed data in a scalable cluster system and computer program for such data storage system
[patent_app_type] => utility
[patent_app_number] => 15/623735
[patent_app_country] => US
[patent_app_date] => 2017-06-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 31
[patent_no_of_words] => 46143
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 303
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15623735
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/623735 | Data storage system and process for data compression of distributed data in a scalable cluster system and computer program for such data storage system | Jun 14, 2017 | Issued |
Array
(
[id] => 14298871
[patent_doc_number] => 10289562
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-05-14
[patent_title] => Incorporating purge history into least-recently-used states of a translation lookaside buffer
[patent_app_type] => utility
[patent_app_number] => 15/623755
[patent_app_country] => US
[patent_app_date] => 2017-06-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5839
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 180
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15623755
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/623755 | Incorporating purge history into least-recently-used states of a translation lookaside buffer | Jun 14, 2017 | Issued |
Array
(
[id] => 14364359
[patent_doc_number] => 10303483
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-05-28
[patent_title] => Arithmetic processing unit and control method for arithmetic processing unit
[patent_app_type] => utility
[patent_app_number] => 15/616171
[patent_app_country] => US
[patent_app_date] => 2017-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 19
[patent_no_of_words] => 15476
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 241
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15616171
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/616171 | Arithmetic processing unit and control method for arithmetic processing unit | Jun 6, 2017 | Issued |
Array
(
[id] => 13332781
[patent_doc_number] => 20180217928
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-08-02
[patent_title] => DATA STORAGE DEVICE AND OPERATING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 15/615954
[patent_app_country] => US
[patent_app_date] => 2017-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6065
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15615954
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/615954 | Data storage device and operating method thereof | Jun 6, 2017 | Issued |
Array
(
[id] => 14886971
[patent_doc_number] => 10423528
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-09-24
[patent_title] => Operation processing device, information processing apparatus, and control method for operation processing device
[patent_app_type] => utility
[patent_app_number] => 15/616102
[patent_app_country] => US
[patent_app_date] => 2017-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 51
[patent_figures_cnt] => 51
[patent_no_of_words] => 39260
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 189
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15616102
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/616102 | Operation processing device, information processing apparatus, and control method for operation processing device | Jun 6, 2017 | Issued |