Search

Denise Tran

Examiner (ID: 13667, Phone: (571)272-4189 , Office: P/2138 )

Most Active Art Unit
2138
Art Unit(s)
2318, 2138, 2185, 2188, 2186, 2302, 2752, 2189, 2312
Total Applications
671
Issued Applications
551
Pending Applications
19
Abandoned Applications
103

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12173774 [patent_doc_number] => 09891916 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-13 [patent_title] => 'Dynamically updating hardware prefetch trait to exclusive or shared in multi-memory access agent system' [patent_app_type] => utility [patent_app_number] => 14/624981 [patent_app_country] => US [patent_app_date] => 2015-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 7489 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14624981 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/624981
Dynamically updating hardware prefetch trait to exclusive or shared in multi-memory access agent system Feb 17, 2015 Issued
Array ( [id] => 11889727 [patent_doc_number] => 09760288 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-12 [patent_title] => 'Determining causes of external fragmentation of memory' [patent_app_type] => utility [patent_app_number] => 14/624990 [patent_app_country] => US [patent_app_date] => 2015-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6780 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14624990 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/624990
Determining causes of external fragmentation of memory Feb 17, 2015 Issued
Array ( [id] => 10300798 [patent_doc_number] => 20150185798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-02 [patent_title] => 'POWER INTERRUPT MANAGEMENT' [patent_app_type] => utility [patent_app_number] => 14/624692 [patent_app_country] => US [patent_app_date] => 2015-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5894 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14624692 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/624692
Power interrupt management Feb 17, 2015 Issued
Array ( [id] => 11752153 [patent_doc_number] => 09710165 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-07-18 [patent_title] => 'Identifying volume candidates for space reclamation' [patent_app_type] => utility [patent_app_number] => 14/624752 [patent_app_country] => US [patent_app_date] => 2015-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7321 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14624752 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/624752
Identifying volume candidates for space reclamation Feb 17, 2015 Issued
Array ( [id] => 11860950 [patent_doc_number] => 09740633 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-22 [patent_title] => 'Updatable address lookup application program interface' [patent_app_type] => utility [patent_app_number] => 14/591045 [patent_app_country] => US [patent_app_date] => 2015-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7051 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14591045 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/591045
Updatable address lookup application program interface Jan 6, 2015 Issued
Array ( [id] => 10308354 [patent_doc_number] => 20150193355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-09 [patent_title] => 'PARTITIONED CACHE REPLACEMENT ALGORITHM' [patent_app_type] => utility [patent_app_number] => 14/591322 [patent_app_country] => US [patent_app_date] => 2015-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5389 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14591322 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/591322
PARTITIONED CACHE REPLACEMENT ALGORITHM Jan 6, 2015 Abandoned
Array ( [id] => 10309196 [patent_doc_number] => 20150194197 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-09 [patent_title] => 'DYNAMIC RANDOM ACCESS MEMORY (DRAM) BACKCHANNEL COMMUNICATION SYSTEMS AND METHODS' [patent_app_type] => utility [patent_app_number] => 14/591056 [patent_app_country] => US [patent_app_date] => 2015-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5751 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14591056 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/591056
Dynamic random access memory (DRAM) backchannel communication systems and methods Jan 6, 2015 Issued
Array ( [id] => 10708964 [patent_doc_number] => 20160055111 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-25 [patent_title] => 'USING A CREDITS AVAILABLE VALUE IN DETERMINING WHETHER TO ISSUE A PPI ALLOCATION REQUEST TO A PACKET ENGINE' [patent_app_type] => utility [patent_app_number] => 14/591003 [patent_app_country] => US [patent_app_date] => 2015-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 19241 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14591003 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/591003
Using a credits available value in determining whether to issue a PPI allocation request to a packet engine Jan 6, 2015 Issued
Array ( [id] => 10708964 [patent_doc_number] => 20160055111 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-25 [patent_title] => 'USING A CREDITS AVAILABLE VALUE IN DETERMINING WHETHER TO ISSUE A PPI ALLOCATION REQUEST TO A PACKET ENGINE' [patent_app_type] => utility [patent_app_number] => 14/591003 [patent_app_country] => US [patent_app_date] => 2015-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 19241 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14591003 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/591003
Using a credits available value in determining whether to issue a PPI allocation request to a packet engine Jan 6, 2015 Issued
Array ( [id] => 10708966 [patent_doc_number] => 20160055112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-25 [patent_title] => 'RETURN AVAILABLE PPI CREDITS COMMAND' [patent_app_type] => utility [patent_app_number] => 14/590920 [patent_app_country] => US [patent_app_date] => 2015-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 19254 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14590920 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/590920
Return available PPI credits command Jan 5, 2015 Issued
Array ( [id] => 11345130 [patent_doc_number] => 09529535 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-27 [patent_title] => 'Storage system and method of control for storage system' [patent_app_type] => utility [patent_app_number] => 14/569923 [patent_app_country] => US [patent_app_date] => 2014-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 21620 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 541 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14569923 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/569923
Storage system and method of control for storage system Dec 14, 2014 Issued
Array ( [id] => 10204129 [patent_doc_number] => 20150089117 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-26 [patent_title] => 'COMPUTER SYSTEM, MEMORY MANAGEMENT METHOD AND PROGRAM THEREOF' [patent_app_type] => utility [patent_app_number] => 14/560712 [patent_app_country] => US [patent_app_date] => 2014-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 13300 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14560712 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/560712
Computer system, memory management method and program thereof Dec 3, 2014 Issued
Array ( [id] => 11326853 [patent_doc_number] => 20160357465 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-08 [patent_title] => 'COPY PROCESSING MANAGEMENT SYSTEM AND COPY PROCESSING MANAGEMENT METHOD' [patent_app_type] => utility [patent_app_number] => 15/120846 [patent_app_country] => US [patent_app_date] => 2014-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8471 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15120846 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/120846
Copy processing management system and copy processing management method Nov 6, 2014 Issued
Array ( [id] => 13096665 [patent_doc_number] => 10067673 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-04 [patent_title] => Management system for storage system [patent_app_type] => utility [patent_app_number] => 15/120865 [patent_app_country] => US [patent_app_date] => 2014-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 42 [patent_no_of_words] => 22524 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15120865 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/120865
Management system for storage system Sep 28, 2014 Issued
Array ( [id] => 11333000 [patent_doc_number] => 09524246 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-20 [patent_title] => 'Resetting memory locks in a transactional memory system' [patent_app_type] => utility [patent_app_number] => 14/481997 [patent_app_country] => US [patent_app_date] => 2014-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5875 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14481997 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/481997
Resetting memory locks in a transactional memory system Sep 9, 2014 Issued
Array ( [id] => 10665668 [patent_doc_number] => 20160011812 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-14 [patent_title] => 'Memory System' [patent_app_type] => utility [patent_app_number] => 14/481622 [patent_app_country] => US [patent_app_date] => 2014-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8888 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14481622 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/481622
Memory System Sep 8, 2014 Abandoned
Array ( [id] => 11510034 [patent_doc_number] => 09601197 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-21 [patent_title] => 'Memory system and control method' [patent_app_type] => utility [patent_app_number] => 14/481437 [patent_app_country] => US [patent_app_date] => 2014-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 12802 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14481437 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/481437
Memory system and control method Sep 8, 2014 Issued
Array ( [id] => 11482156 [patent_doc_number] => 09588701 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-07 [patent_title] => 'Multi-stage programming at a storage device using multiple instructions from a host' [patent_app_type] => utility [patent_app_number] => 14/481308 [patent_app_country] => US [patent_app_date] => 2014-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7558 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14481308 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/481308
Multi-stage programming at a storage device using multiple instructions from a host Sep 8, 2014 Issued
Array ( [id] => 10724503 [patent_doc_number] => 20160070651 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-10 [patent_title] => 'INSTRUCTION AND LOGIC FOR A CACHE PREFETCHER AND DATALESS FILL BUFFER' [patent_app_type] => utility [patent_app_number] => 14/481266 [patent_app_country] => US [patent_app_date] => 2014-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 16646 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14481266 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/481266
Instruction and logic for a cache prefetcher and dataless fill buffer Sep 8, 2014 Issued
Array ( [id] => 11208790 [patent_doc_number] => 09438424 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-06 [patent_title] => 'Methods, apparatus, and systems for secure demand paging and other paging operations for processor devices' [patent_app_type] => utility [patent_app_number] => 14/458592 [patent_app_country] => US [patent_app_date] => 2014-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 34 [patent_no_of_words] => 58936 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14458592 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/458592
Methods, apparatus, and systems for secure demand paging and other paging operations for processor devices Aug 12, 2014 Issued
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