
Dennis Y. Myint
Examiner (ID: 4556)
| Most Active Art Unit | 2162 |
| Art Unit(s) | 2162 |
| Total Applications | 246 |
| Issued Applications | 165 |
| Pending Applications | 11 |
| Abandoned Applications | 70 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5319879
[patent_doc_number] => 20090057869
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-03-05
[patent_title] => 'CO-PACKAGED HIGH-SIDE AND LOW-SIDE NMOSFETS FOR EFFICIENT DC-DC POWER CONVERSION'
[patent_app_type] => utility
[patent_app_number] => 11/849160
[patent_app_country] => US
[patent_app_date] => 2007-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 6489
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0057/20090057869.pdf
[firstpage_image] =>[orig_patent_app_number] => 11849160
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/849160 | CO-PACKAGED HIGH-SIDE AND LOW-SIDE NMOSFETS FOR EFFICIENT DC-DC POWER CONVERSION | Aug 30, 2007 | Abandoned |
Array
(
[id] => 5319865
[patent_doc_number] => 20090057855
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-03-05
[patent_title] => 'SEMICONDUCTOR DIE PACKAGE INCLUDING STAND OFF STRUCTURES'
[patent_app_type] => utility
[patent_app_number] => 11/847670
[patent_app_country] => US
[patent_app_date] => 2007-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 5296
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
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[pdf_file] => publications/A1/0057/20090057855.pdf
[firstpage_image] =>[orig_patent_app_number] => 11847670
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/847670 | SEMICONDUCTOR DIE PACKAGE INCLUDING STAND OFF STRUCTURES | Aug 29, 2007 | Abandoned |
Array
(
[id] => 5319877
[patent_doc_number] => 20090057867
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-03-05
[patent_title] => 'Integrated Circuit Package with Passive Component'
[patent_app_type] => utility
[patent_app_number] => 11/847470
[patent_app_country] => US
[patent_app_date] => 2007-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 1977
[patent_no_of_claims] => 21
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[pdf_file] => publications/A1/0057/20090057867.pdf
[firstpage_image] =>[orig_patent_app_number] => 11847470
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/847470 | Integrated Circuit Package with Passive Component | Aug 29, 2007 | Abandoned |
Array
(
[id] => 8270304
[patent_doc_number] => 08211806
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-07-03
[patent_title] => 'Method of fabricating integrated circuit with small pitch'
[patent_app_type] => utility
[patent_app_number] => 11/846900
[patent_app_country] => US
[patent_app_date] => 2007-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 21
[patent_no_of_words] => 1920
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11846900
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/846900 | Method of fabricating integrated circuit with small pitch | Aug 28, 2007 | Issued |
Array
(
[id] => 4768753
[patent_doc_number] => 20080054409
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-03-06
[patent_title] => 'FABRICATING METHOD OF SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 11/844660
[patent_app_country] => US
[patent_app_date] => 2007-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 989
[patent_no_of_claims] => 20
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[pdf_file] => publications/A1/0054/20080054409.pdf
[firstpage_image] =>[orig_patent_app_number] => 11844660
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/844660 | FABRICATING METHOD OF SEMICONDUCTOR DEVICE | Aug 23, 2007 | Abandoned |
Array
(
[id] => 5334575
[patent_doc_number] => 20090051039
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-02-26
[patent_title] => 'THROUGH-SUBSTRATE VIA FOR SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 11/844650
[patent_app_country] => US
[patent_app_date] => 2007-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 4633
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[pdf_file] => publications/A1/0051/20090051039.pdf
[firstpage_image] =>[orig_patent_app_number] => 11844650
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/844650 | Through-substrate via for semiconductor device | Aug 23, 2007 | Issued |
Array
(
[id] => 7503337
[patent_doc_number] => 08034702
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-10-11
[patent_title] => 'Methods of forming through substrate interconnects'
[patent_app_type] => utility
[patent_app_number] => 11/840120
[patent_app_country] => US
[patent_app_date] => 2007-08-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 21
[patent_no_of_words] => 4560
[patent_no_of_claims] => 23
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[pdf_file] => patents/08/034/08034702.pdf
[firstpage_image] =>[orig_patent_app_number] => 11840120
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/840120 | Methods of forming through substrate interconnects | Aug 15, 2007 | Issued |
Array
(
[id] => 151392
[patent_doc_number] => 07682924
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-03-23
[patent_title] => 'Methods of forming a plurality of capacitors'
[patent_app_type] => utility
[patent_app_number] => 11/838070
[patent_app_country] => US
[patent_app_date] => 2007-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
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[patent_no_of_words] => 4462
[patent_no_of_claims] => 40
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/682/07682924.pdf
[firstpage_image] =>[orig_patent_app_number] => 11838070
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/838070 | Methods of forming a plurality of capacitors | Aug 12, 2007 | Issued |
Array
(
[id] => 5416470
[patent_doc_number] => 20090042357
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-02-12
[patent_title] => 'Method of selective oxygen implantation to dielectrically isolate semiconductor devices using no extra masks'
[patent_app_type] => utility
[patent_app_number] => 11/891170
[patent_app_country] => US
[patent_app_date] => 2007-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => publications/A1/0042/20090042357.pdf
[firstpage_image] =>[orig_patent_app_number] => 11891170
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/891170 | Method of selective oxygen implantation to dielectrically isolate semiconductor devices using no extra masks | Aug 8, 2007 | Issued |
Array
(
[id] => 133913
[patent_doc_number] => 07696607
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-04-13
[patent_title] => 'Semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/889210
[patent_app_country] => US
[patent_app_date] => 2007-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/696/07696607.pdf
[firstpage_image] =>[orig_patent_app_number] => 11889210
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/889210 | Semiconductor device | Aug 8, 2007 | Issued |
Array
(
[id] => 4553180
[patent_doc_number] => 07960814
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-06-14
[patent_title] => 'Stress relief of a semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/835680
[patent_app_country] => US
[patent_app_date] => 2007-08-08
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[pdf_file] => patents/07/960/07960814.pdf
[firstpage_image] =>[orig_patent_app_number] => 11835680
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/835680 | Stress relief of a semiconductor device | Aug 7, 2007 | Issued |
Array
(
[id] => 45175
[patent_doc_number] => 07777318
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-08-17
[patent_title] => 'Wafer level packaging integrated hydrogen getter'
[patent_app_type] => utility
[patent_app_number] => 11/782460
[patent_app_country] => US
[patent_app_date] => 2007-07-24
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/777/07777318.pdf
[firstpage_image] =>[orig_patent_app_number] => 11782460
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/782460 | Wafer level packaging integrated hydrogen getter | Jul 23, 2007 | Issued |
Array
(
[id] => 5043756
[patent_doc_number] => 20070262427
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-11-15
[patent_title] => 'SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 11/781330
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[firstpage_image] =>[orig_patent_app_number] => 11781330
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/781330 | SEMICONDUCTOR DEVICE | Jul 22, 2007 | Abandoned |
Array
(
[id] => 4749234
[patent_doc_number] => 20080157305
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-03
[patent_title] => 'CHIP PACKAGE STRUCTURE'
[patent_app_type] => utility
[patent_app_number] => 11/781420
[patent_app_country] => US
[patent_app_date] => 2007-07-23
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[firstpage_image] =>[orig_patent_app_number] => 11781420
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/781420 | CHIP PACKAGE STRUCTURE | Jul 22, 2007 | Abandoned |
Array
(
[id] => 5288139
[patent_doc_number] => 20090020869
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-01-22
[patent_title] => 'INTERCONNECT JOINT'
[patent_app_type] => utility
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[pdf_file] => publications/A1/0020/20090020869.pdf
[firstpage_image] =>[orig_patent_app_number] => 11779110
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/779110 | INTERCONNECT JOINT | Jul 16, 2007 | Abandoned |
Array
(
[id] => 4768778
[patent_doc_number] => 20080054434
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-03-06
[patent_title] => 'SEMICONDUCTOR STACK PACKAGE FOR OPTIMAL PACKAGING OF COMPONENTS HAVING INTERCONNECTIONS'
[patent_app_type] => utility
[patent_app_number] => 11/777420
[patent_app_country] => US
[patent_app_date] => 2007-07-13
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[pdf_file] => publications/A1/0054/20080054434.pdf
[firstpage_image] =>[orig_patent_app_number] => 11777420
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/777420 | SEMICONDUCTOR STACK PACKAGE FOR OPTIMAL PACKAGING OF COMPONENTS HAVING INTERCONNECTIONS | Jul 12, 2007 | Abandoned |
Array
(
[id] => 4648771
[patent_doc_number] => 20080036026
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-02-14
[patent_title] => 'METAL LINE OF IMAGE SENSOR'
[patent_app_type] => utility
[patent_app_number] => 11/775635
[patent_app_country] => US
[patent_app_date] => 2007-07-10
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[pdf_file] => publications/A1/0036/20080036026.pdf
[firstpage_image] =>[orig_patent_app_number] => 11775635
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/775635 | METAL LINE OF IMAGE SENSOR | Jul 9, 2007 | Abandoned |
Array
(
[id] => 4907222
[patent_doc_number] => 20080017988
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-01-24
[patent_title] => 'SEMICONDUCTOR DEVICE HAVING COPPER METAL LINE AND METHOD OF FORMING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 11/775060
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/775060 | Semiconductor device having copper metal line and method of forming the same | Jul 8, 2007 | Issued |
Array
(
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[patent_title] => 'Encapsulated microcomponent equipped with at least one getter'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/774200 | Encapsulated microcomponent equipped with at least one getter | Jul 5, 2007 | Issued |
Array
(
[id] => 5346203
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[pdf_file] => publications/A1/0001/20090001564.pdf
[firstpage_image] =>[orig_patent_app_number] => 11771990
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/771990 | Package substrate dynamic pressure structure | Jun 28, 2007 | Issued |