Search

Deoram Persaud

Examiner (ID: 12323, Phone: (571)270-5476 , Office: P/2882 )

Most Active Art Unit
2882
Art Unit(s)
2882
Total Applications
891
Issued Applications
642
Pending Applications
83
Abandoned Applications
181

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20550759 [patent_doc_number] => 12561553 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-24 [patent_title] => In-memory resonator network for factorizing hyper vectors [patent_app_type] => utility [patent_app_number] => 17/655026 [patent_app_country] => US [patent_app_date] => 2022-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 5104 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17655026 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/655026
In-memory resonator network for factorizing hyper vectors Mar 15, 2022 Issued
Array ( [id] => 20609828 [patent_doc_number] => 12585430 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-24 [patent_title] => Floating-point conversion with denormalization [patent_app_type] => utility [patent_app_number] => 17/696448 [patent_app_country] => US [patent_app_date] => 2022-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17696448 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/696448
Floating-point conversion with denormalization Mar 15, 2022 Issued
Array ( [id] => 18630251 [patent_doc_number] => 20230289143 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-14 [patent_title] => MEMORY DEVICE AND COMPUTING METHOD [patent_app_type] => utility [patent_app_number] => 17/693406 [patent_app_country] => US [patent_app_date] => 2022-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7020 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17693406 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/693406
MEMORY DEVICE AND COMPUTING METHOD Mar 12, 2022 Pending
Array ( [id] => 17737055 [patent_doc_number] => 20220222515 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => INTEGRATED CIRCUIT CHIP APPARATUS [patent_app_type] => utility [patent_app_number] => 17/688853 [patent_app_country] => US [patent_app_date] => 2022-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 36035 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17688853 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/688853
Integrated circuit chip apparatus Mar 6, 2022 Issued
Array ( [id] => 17737054 [patent_doc_number] => 20220222514 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => INTEGRATED CIRCUIT CHIP APPARATUS [patent_app_type] => utility [patent_app_number] => 17/688844 [patent_app_country] => US [patent_app_date] => 2022-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 36029 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17688844 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/688844
Integrated circuit chip apparatus Mar 6, 2022 Issued
Array ( [id] => 18148659 [patent_doc_number] => 20230022516 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-26 [patent_title] => COMPUTE-IN-MEMORY SYSTEMS AND METHODS WITH CONFIGURABLE INPUT AND SUMMING UNITS [patent_app_type] => utility [patent_app_number] => 17/686147 [patent_app_country] => US [patent_app_date] => 2022-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6890 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17686147 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/686147
COMPUTE-IN-MEMORY SYSTEMS AND METHODS WITH CONFIGURABLE INPUT AND SUMMING UNITS Mar 2, 2022 Pending
Array ( [id] => 18270775 [patent_doc_number] => 20230092017 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => COMPUTING DEVICE AND METHOD [patent_app_type] => utility [patent_app_number] => 17/678339 [patent_app_country] => US [patent_app_date] => 2022-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7476 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17678339 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/678339
Computing device with pixel unshuffle and pixel shuffle operations and computing method therefor Feb 22, 2022 Issued
Array ( [id] => 20703376 [patent_doc_number] => 12626089 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-12 [patent_title] => Device and method with multidimensional vector neural network [patent_app_type] => utility [patent_app_number] => 17/591114 [patent_app_country] => US [patent_app_date] => 2022-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 11638 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17591114 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/591114
Device and method with multidimensional vector neural network Feb 1, 2022 Issued
Array ( [id] => 17598286 [patent_doc_number] => 20220147860 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-12 [patent_title] => QUANTUM PHASE ESTIMATION OF MULTIPLE EIGENVALUES [patent_app_type] => utility [patent_app_number] => 17/584041 [patent_app_country] => US [patent_app_date] => 2022-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7288 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17584041 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/584041
Quantum phase estimation of multiple eigenvalues Jan 24, 2022 Issued
Array ( [id] => 17581072 [patent_doc_number] => 20220137927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => PROCESSING COMPONENT, DATA PROCESSING METHOD, AND RELATED DEVICE [patent_app_type] => utility [patent_app_number] => 17/579489 [patent_app_country] => US [patent_app_date] => 2022-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19779 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17579489 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/579489
Processing component that includes an arithmetic and logic unit (ALU), data processing method applied to the processing component, and related device Jan 18, 2022 Issued
Array ( [id] => 20317172 [patent_doc_number] => 12455723 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-28 [patent_title] => MAC processing pipeline having activation circuitry, and methods of operating same [patent_app_type] => utility [patent_app_number] => 17/577454 [patent_app_country] => US [patent_app_date] => 2022-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 34 [patent_no_of_words] => 15840 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17577454 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/577454
MAC processing pipeline having activation circuitry, and methods of operating same Jan 17, 2022 Issued
Array ( [id] => 20550600 [patent_doc_number] => 12561394 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-24 [patent_title] => Method for synthesizing a product of Pauli rotations [patent_app_type] => utility [patent_app_number] => 17/573720 [patent_app_country] => US [patent_app_date] => 2022-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 1086 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17573720 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/573720
Method for synthesizing a product of Pauli rotations Jan 11, 2022 Issued
Array ( [id] => 18965980 [patent_doc_number] => 11899746 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => Circuitry for high-bandwidth, low-latency machine learning [patent_app_type] => utility [patent_app_number] => 17/560950 [patent_app_country] => US [patent_app_date] => 2021-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 33 [patent_no_of_words] => 11393 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17560950 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/560950
Circuitry for high-bandwidth, low-latency machine learning Dec 22, 2021 Issued
Array ( [id] => 18982152 [patent_doc_number] => 11907326 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-02-20 [patent_title] => Systems and method for determining frequency coefficients of signals [patent_app_type] => utility [patent_app_number] => 17/559475 [patent_app_country] => US [patent_app_date] => 2021-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 20490 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17559475 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/559475
Systems and method for determining frequency coefficients of signals Dec 21, 2021 Issued
Array ( [id] => 19507037 [patent_doc_number] => 12118463 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-10-15 [patent_title] => Weight value decoder of neural network inference circuit [patent_app_type] => utility [patent_app_number] => 17/550177 [patent_app_country] => US [patent_app_date] => 2021-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 54 [patent_figures_cnt] => 55 [patent_no_of_words] => 54720 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17550177 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/550177
Weight value decoder of neural network inference circuit Dec 13, 2021 Issued
Array ( [id] => 17899172 [patent_doc_number] => 20220308834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => FLOATING POINT MULTIPLY-ADD, ACCUMULATE UNIT WITH EXCEPTION PROCESSING [patent_app_type] => utility [patent_app_number] => 17/534376 [patent_app_country] => US [patent_app_date] => 2021-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20242 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17534376 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/534376
Floating point multiply-add, accumulate unit with exception processing Nov 22, 2021 Issued
Array ( [id] => 20623903 [patent_doc_number] => 12591411 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-31 [patent_title] => System and method to accelerate graph feature extraction [patent_app_type] => utility [patent_app_number] => 17/530452 [patent_app_country] => US [patent_app_date] => 2021-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 13707 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17530452 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/530452
System and method to accelerate graph feature extraction Nov 17, 2021 Issued
Array ( [id] => 20595495 [patent_doc_number] => 12579213 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-17 [patent_title] => Bias scaling for n-bit constrained hardware acceleration [patent_app_type] => utility [patent_app_number] => 17/528472 [patent_app_country] => US [patent_app_date] => 2021-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 1145 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 372 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17528472 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/528472
Bias scaling for n-bit constrained hardware acceleration Nov 16, 2021 Issued
Array ( [id] => 17644089 [patent_doc_number] => 20220171827 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-02 [patent_title] => SPARSE MATRIX MULTIPLICATION ACCELERATION MECHANISM [patent_app_type] => utility [patent_app_number] => 17/527324 [patent_app_country] => US [patent_app_date] => 2021-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28329 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17527324 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/527324
Sparse matrix multiplication acceleration mechanism Nov 15, 2021 Issued
Array ( [id] => 17862039 [patent_doc_number] => 11443198 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-09-13 [patent_title] => Directed acyclic graph machine learning system [patent_app_type] => utility [patent_app_number] => 17/522062 [patent_app_country] => US [patent_app_date] => 2021-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 11026 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17522062 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/522062
Directed acyclic graph machine learning system Nov 8, 2021 Issued
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