Search

Derrick Edward Holland

Examiner (ID: 404, Phone: (571)272-3089 , Office: P/2912 )

Most Active Art Unit
2912
Art Unit(s)
2912
Total Applications
3302
Issued Applications
3253
Pending Applications
21
Abandoned Applications
28

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3592448 [patent_doc_number] => 05499352 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-12 [patent_title] => 'Floating point register alias table FXCH and retirement floating point register array' [patent_app_type] => 1 [patent_app_number] => 8/129687 [patent_app_country] => US [patent_app_date] => 1993-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 32 [patent_no_of_words] => 32657 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/499/05499352.pdf [firstpage_image] =>[orig_patent_app_number] => 129687 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/129687
Floating point register alias table FXCH and retirement floating point register array Sep 29, 1993 Issued
08/120221 RANDOM ACCESS MEMORY WITH DIVIDED MEMORY BANKS AND DATA READ/WRITE ARCHITECTURE THEREFOR Sep 13, 1993 Abandoned
Array ( [id] => 3432352 [patent_doc_number] => 05479627 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-26 [patent_title] => 'Virtual address to physical address translation cache that supports multiple page sizes' [patent_app_type] => 1 [patent_app_number] => 8/118398 [patent_app_country] => US [patent_app_date] => 1993-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7973 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 345 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/479/05479627.pdf [firstpage_image] =>[orig_patent_app_number] => 118398 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/118398
Virtual address to physical address translation cache that supports multiple page sizes Sep 7, 1993 Issued
Array ( [id] => 3069248 [patent_doc_number] => 05357620 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-18 [patent_title] => 'Bit addressing system' [patent_app_type] => 1 [patent_app_number] => 8/115125 [patent_app_country] => US [patent_app_date] => 1993-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3752 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/357/05357620.pdf [firstpage_image] =>[orig_patent_app_number] => 115125 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/115125
Bit addressing system Aug 31, 1993 Issued
Array ( [id] => 3497635 [patent_doc_number] => 05426764 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-20 [patent_title] => 'Cache miss prediction apparatus with priority encoder for multiple prediction matches and method therefor' [patent_app_type] => 1 [patent_app_number] => 8/111351 [patent_app_country] => US [patent_app_date] => 1993-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5152 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/426/05426764.pdf [firstpage_image] =>[orig_patent_app_number] => 111351 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/111351
Cache miss prediction apparatus with priority encoder for multiple prediction matches and method therefor Aug 23, 1993 Issued
Array ( [id] => 3575778 [patent_doc_number] => 05526501 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-11 [patent_title] => 'Variable accuracy indirect addressing scheme for SIMD multi-processors and apparatus implementing same' [patent_app_type] => 1 [patent_app_number] => 8/106343 [patent_app_country] => US [patent_app_date] => 1993-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1931 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/526/05526501.pdf [firstpage_image] =>[orig_patent_app_number] => 106343 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/106343
Variable accuracy indirect addressing scheme for SIMD multi-processors and apparatus implementing same Aug 11, 1993 Issued
Array ( [id] => 3432337 [patent_doc_number] => 05479626 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-26 [patent_title] => 'Signal processor contexts with elemental and reserved group addressing' [patent_app_type] => 1 [patent_app_number] => 8/095550 [patent_app_country] => US [patent_app_date] => 1993-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 3367 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/479/05479626.pdf [firstpage_image] =>[orig_patent_app_number] => 095550 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/095550
Signal processor contexts with elemental and reserved group addressing Jul 25, 1993 Issued
Array ( [id] => 3532740 [patent_doc_number] => 05490259 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-06 [patent_title] => 'Logical-to-real address translation based on selective use of first and second TLBs' [patent_app_type] => 1 [patent_app_number] => 8/093969 [patent_app_country] => US [patent_app_date] => 1993-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5035 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/490/05490259.pdf [firstpage_image] =>[orig_patent_app_number] => 093969 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/093969
Logical-to-real address translation based on selective use of first and second TLBs Jul 20, 1993 Issued
Array ( [id] => 3495174 [patent_doc_number] => 05426607 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-20 [patent_title] => 'Redundant circuit for memory having redundant block operatively connected to special one of normal blocks' [patent_app_type] => 1 [patent_app_number] => 8/091732 [patent_app_country] => US [patent_app_date] => 1993-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1431 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/426/05426607.pdf [firstpage_image] =>[orig_patent_app_number] => 091732 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/091732
Redundant circuit for memory having redundant block operatively connected to special one of normal blocks Jul 13, 1993 Issued
Array ( [id] => 3138553 [patent_doc_number] => 05437018 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-25 [patent_title] => 'Emulation of semiconductor and magnetic auxiliary storage devices with semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 8/086417 [patent_app_country] => US [patent_app_date] => 1993-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 6454 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/437/05437018.pdf [firstpage_image] =>[orig_patent_app_number] => 086417 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/086417
Emulation of semiconductor and magnetic auxiliary storage devices with semiconductor memory Jul 1, 1993 Issued
Array ( [id] => 3125921 [patent_doc_number] => 05414824 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-09 [patent_title] => 'Apparatus and method for accessing a split line in a high speed cache' [patent_app_type] => 1 [patent_app_number] => 8/087637 [patent_app_country] => US [patent_app_date] => 1993-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 10885 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/414/05414824.pdf [firstpage_image] =>[orig_patent_app_number] => 087637 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/087637
Apparatus and method for accessing a split line in a high speed cache Jun 29, 1993 Issued
Array ( [id] => 3127716 [patent_doc_number] => 05396608 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-07 [patent_title] => 'Method and apparatus for accessing variable length words in a memory array' [patent_app_type] => 1 [patent_app_number] => 8/083619 [patent_app_country] => US [patent_app_date] => 1993-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6262 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/396/05396608.pdf [firstpage_image] =>[orig_patent_app_number] => 083619 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/083619
Method and apparatus for accessing variable length words in a memory array Jun 27, 1993 Issued
08/082161 DYANAMIC RANDOM ACCESS MEMORY DEVICE Jun 27, 1993 Pending
Array ( [id] => 3058861 [patent_doc_number] => 05335336 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-02 [patent_title] => 'Memory device having refresh mode returning previous page address for resumed page mode' [patent_app_type] => 1 [patent_app_number] => 8/079852 [patent_app_country] => US [patent_app_date] => 1993-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 8848 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/335/05335336.pdf [firstpage_image] =>[orig_patent_app_number] => 079852 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/079852
Memory device having refresh mode returning previous page address for resumed page mode Jun 21, 1993 Issued
Array ( [id] => 3032214 [patent_doc_number] => 05289409 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-02-22 [patent_title] => 'Bipolar transistor memory cell and method' [patent_app_type] => 1 [patent_app_number] => 8/073457 [patent_app_country] => US [patent_app_date] => 1993-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1709 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/289/05289409.pdf [firstpage_image] =>[orig_patent_app_number] => 073457 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/073457
Bipolar transistor memory cell and method Jun 6, 1993 Issued
Array ( [id] => 3453257 [patent_doc_number] => 05398322 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-14 [patent_title] => 'Number theory mapping generator for addressing matrix structures' [patent_app_type] => 1 [patent_app_number] => 7/958319 [patent_app_country] => US [patent_app_date] => 1993-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 4187 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/398/05398322.pdf [firstpage_image] =>[orig_patent_app_number] => 958319 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/958319
Number theory mapping generator for addressing matrix structures May 17, 1993 Issued
08/064189 RISC PROCESSOR UTILIZING ADDRESS BIT PREDECODING FOR A SEGMENTED CACHE MEMORY May 16, 1993 Pending
Array ( [id] => 3451467 [patent_doc_number] => 05398201 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-14 [patent_title] => 'Bit-line drive circuit for a semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 8/053330 [patent_app_country] => US [patent_app_date] => 1993-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 30 [patent_no_of_words] => 12206 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/398/05398201.pdf [firstpage_image] =>[orig_patent_app_number] => 053330 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/053330
Bit-line drive circuit for a semiconductor memory Apr 27, 1993 Issued
Array ( [id] => 3049817 [patent_doc_number] => 05301288 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-05 [patent_title] => 'Virtual memory management and allocation arrangement for digital data processing system' [patent_app_type] => 1 [patent_app_number] => 8/053843 [patent_app_country] => US [patent_app_date] => 1993-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 21 [patent_no_of_words] => 13196 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/301/05301288.pdf [firstpage_image] =>[orig_patent_app_number] => 053843 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/053843
Virtual memory management and allocation arrangement for digital data processing system Apr 26, 1993 Issued
Array ( [id] => 3576697 [patent_doc_number] => 05483644 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-09 [patent_title] => 'Method for increasing cacheable address space in a second level cache' [patent_app_type] => 1 [patent_app_number] => 8/048710 [patent_app_country] => US [patent_app_date] => 1993-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1592 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/483/05483644.pdf [firstpage_image] =>[orig_patent_app_number] => 048710 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/048710
Method for increasing cacheable address space in a second level cache Apr 14, 1993 Issued
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