Application number | Title of the application | Filing Date | Status |
---|
Array
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Array
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Array
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[patent_kind] => NA
[patent_issue_date] => 1995-07-04
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[patent_app_number] => 8/029068
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Array
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[patent_kind] => NA
[patent_issue_date] => 1995-04-04
[patent_title] => 'Multiprocessing system having a single translation lookaside buffer with reduced processor overhead'
[patent_app_type] => 1
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Array
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[patent_doc_number] => 05332722
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-07-26
[patent_title] => 'Nonvolatile memory element composed of combined superconductor ring and MOSFET'
[patent_app_type] => 1
[patent_app_number] => 8/028632
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Array
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[patent_kind] => NA
[patent_issue_date] => 1996-01-02
[patent_title] => 'Information processing system having an address translation table loaded with main/expanded memory presence bits'
[patent_app_type] => 1
[patent_app_number] => 8/020369
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Array
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[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-12-26
[patent_title] => 'Multiprocessor cache memory unit selectively enabling bus snooping during in-circuit emulation'
[patent_app_type] => 1
[patent_app_number] => 8/019227
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Array
(
[id] => 3064710
[patent_doc_number] => 05325507
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-06-28
[patent_title] => 'Translation lookaside buffer shutdown scheme'
[patent_app_type] => 1
[patent_app_number] => 8/019541
[patent_app_country] => US
[patent_app_date] => 1993-02-18
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[firstpage_image] =>[orig_patent_app_number] => 019541
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/019541 | Translation lookaside buffer shutdown scheme | Feb 17, 1993 | Issued |
Array
(
[id] => 3473345
[patent_doc_number] => 05392411
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-02-21
[patent_title] => 'Dual-array register file with overlapping window registers'
[patent_app_type] => 1
[patent_app_number] => 8/013105
[patent_app_country] => US
[patent_app_date] => 1993-02-03
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[firstpage_image] =>[orig_patent_app_number] => 013105
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/013105 | Dual-array register file with overlapping window registers | Feb 2, 1993 | Issued |
08/012800 | DIVIDED WORDLINE MEMORY ARRANGEMENT HAVING OVERLAPPING ACTIVATION OF WORD LINES DURING CONTINUOUS ACCESS CYCLE | Feb 1, 1993 | Abandoned |
Array
(
[id] => 2973371
[patent_doc_number] => 05274596
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-12-28
[patent_title] => 'Dynamic semiconductor memory device having simultaneous operation of adjacent blocks'
[patent_app_type] => 1
[patent_app_number] => 8/007012
[patent_app_country] => US
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Array
(
[id] => 3454263
[patent_doc_number] => 05430857
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-07-04
[patent_title] => 'Method and apparatus for translating logical addresses into physical addresses using odd/even translation tables'
[patent_app_type] => 1
[patent_app_number] => 8/000246
[patent_app_country] => US
[patent_app_date] => 1993-01-04
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/000246 | Method and apparatus for translating logical addresses into physical addresses using odd/even translation tables | Jan 3, 1993 | Issued |
07/999689 | DYNAMIC TYPE SEMICONDUCTOR MEMORY DEVICE | Dec 30, 1992 | Abandoned |
Array
(
[id] => 3552564
[patent_doc_number] => 05481687
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-01-02
[patent_title] => 'Method for reducing the number of bits in a binary word representing a series of addresses'
[patent_app_type] => 1
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Array
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[firstpage_image] =>[orig_patent_app_number] => 995400
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/995400 | Memory array based data reorganizer | Dec 17, 1992 | Issued |
Array
(
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[patent_kind] => NA
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[patent_app_type] => 1
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/991017 | System for grouping non-contiguous pages belonging to a storage object for page out | Dec 14, 1992 | Issued |
Array
(
[id] => 3454250
[patent_doc_number] => 05430856
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[patent_kind] => NA
[patent_issue_date] => 1995-07-04
[patent_title] => 'Data processing system simultaneously performing plural translations of virtual addresses having different page sizes'
[patent_app_type] => 1
[patent_app_number] => 7/989829
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Array
(
[id] => 2915308
[patent_doc_number] => 05249265
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-09-28
[patent_title] => 'Structure storage management in a graphics display device'
[patent_app_type] => 1
[patent_app_number] => 7/987983
[patent_app_country] => US
[patent_app_date] => 1992-12-09
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/987983 | Structure storage management in a graphics display device | Dec 8, 1992 | Issued |
07/978606 | SYSTEM FOR DESIGNATING REAL MAIN STORAGE ADDRESSES IN INSTRUCTIONS WHILE DYNAMIC ADDRESS TRANSLATION IS ON | Nov 18, 1992 | Abandoned |
07/976366 | COHERENCY FOR WRITE-BACK CACHE IN A SYSTEM DESIGNED FOR WRITE-THROUGH CACHE | Nov 12, 1992 | Abandoned |