Search

Derrick Edward Holland

Examiner (ID: 404, Phone: (571)272-3089 , Office: P/2912 )

Most Active Art Unit
2912
Art Unit(s)
2912
Total Applications
3302
Issued Applications
3253
Pending Applications
21
Abandoned Applications
28

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3128667 [patent_doc_number] => 05410664 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-25 [patent_title] => 'RAM addressing apparatus with lower power consumption and less noise generation' [patent_app_type] => 1 [patent_app_number] => 8/040667 [patent_app_country] => US [patent_app_date] => 1993-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2390 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/410/05410664.pdf [firstpage_image] =>[orig_patent_app_number] => 040667 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/040667
RAM addressing apparatus with lower power consumption and less noise generation Mar 30, 1993 Issued
Array ( [id] => 3576680 [patent_doc_number] => 05483643 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-09 [patent_title] => 'Control circuit for data transfer between a main memory and a register file' [patent_app_type] => 1 [patent_app_number] => 8/039788 [patent_app_country] => US [patent_app_date] => 1993-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3293 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/483/05483643.pdf [firstpage_image] =>[orig_patent_app_number] => 039788 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/039788
Control circuit for data transfer between a main memory and a register file Mar 29, 1993 Issued
Array ( [id] => 3454204 [patent_doc_number] => 05430853 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-04 [patent_title] => 'Update of control parameters of a direct memory access system without use of associated processor' [patent_app_type] => 1 [patent_app_number] => 8/029068 [patent_app_country] => US [patent_app_date] => 1993-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4712 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/430/05430853.pdf [firstpage_image] =>[orig_patent_app_number] => 029068 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/029068
Update of control parameters of a direct memory access system without use of associated processor Mar 9, 1993 Issued
Array ( [id] => 3437792 [patent_doc_number] => 05404476 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-04 [patent_title] => 'Multiprocessing system having a single translation lookaside buffer with reduced processor overhead' [patent_app_type] => 1 [patent_app_number] => 8/031380 [patent_app_country] => US [patent_app_date] => 1993-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4237 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 376 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/404/05404476.pdf [firstpage_image] =>[orig_patent_app_number] => 031380 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/031380
Multiprocessing system having a single translation lookaside buffer with reduced processor overhead Mar 8, 1993 Issued
Array ( [id] => 3012992 [patent_doc_number] => 05332722 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-26 [patent_title] => 'Nonvolatile memory element composed of combined superconductor ring and MOSFET' [patent_app_type] => 1 [patent_app_number] => 8/028632 [patent_app_country] => US [patent_app_date] => 1993-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4483 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/332/05332722.pdf [firstpage_image] =>[orig_patent_app_number] => 028632 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/028632
Nonvolatile memory element composed of combined superconductor ring and MOSFET Mar 7, 1993 Issued
Array ( [id] => 3552577 [patent_doc_number] => 05481688 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-02 [patent_title] => 'Information processing system having an address translation table loaded with main/expanded memory presence bits' [patent_app_type] => 1 [patent_app_number] => 8/020369 [patent_app_country] => US [patent_app_date] => 1993-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 7353 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 367 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/481/05481688.pdf [firstpage_image] =>[orig_patent_app_number] => 020369 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/020369
Information processing system having an address translation table loaded with main/expanded memory presence bits Feb 21, 1993 Issued
Array ( [id] => 3432461 [patent_doc_number] => 05479634 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-26 [patent_title] => 'Multiprocessor cache memory unit selectively enabling bus snooping during in-circuit emulation' [patent_app_type] => 1 [patent_app_number] => 8/019227 [patent_app_country] => US [patent_app_date] => 1993-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1935 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/479/05479634.pdf [firstpage_image] =>[orig_patent_app_number] => 019227 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/019227
Multiprocessor cache memory unit selectively enabling bus snooping during in-circuit emulation Feb 17, 1993 Issued
Array ( [id] => 3064710 [patent_doc_number] => 05325507 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-06-28 [patent_title] => 'Translation lookaside buffer shutdown scheme' [patent_app_type] => 1 [patent_app_number] => 8/019541 [patent_app_country] => US [patent_app_date] => 1993-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6132 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/325/05325507.pdf [firstpage_image] =>[orig_patent_app_number] => 019541 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/019541
Translation lookaside buffer shutdown scheme Feb 17, 1993 Issued
Array ( [id] => 3473345 [patent_doc_number] => 05392411 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-21 [patent_title] => 'Dual-array register file with overlapping window registers' [patent_app_type] => 1 [patent_app_number] => 8/013105 [patent_app_country] => US [patent_app_date] => 1993-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11052 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 299 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/392/05392411.pdf [firstpage_image] =>[orig_patent_app_number] => 013105 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/013105
Dual-array register file with overlapping window registers Feb 2, 1993 Issued
08/012800 DIVIDED WORDLINE MEMORY ARRANGEMENT HAVING OVERLAPPING ACTIVATION OF WORD LINES DURING CONTINUOUS ACCESS CYCLE Feb 1, 1993 Abandoned
Array ( [id] => 2973371 [patent_doc_number] => 05274596 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-28 [patent_title] => 'Dynamic semiconductor memory device having simultaneous operation of adjacent blocks' [patent_app_type] => 1 [patent_app_number] => 8/007012 [patent_app_country] => US [patent_app_date] => 1993-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3384 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 443 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/274/05274596.pdf [firstpage_image] =>[orig_patent_app_number] => 007012 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/007012
Dynamic semiconductor memory device having simultaneous operation of adjacent blocks Jan 20, 1993 Issued
Array ( [id] => 3454263 [patent_doc_number] => 05430857 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-04 [patent_title] => 'Method and apparatus for translating logical addresses into physical addresses using odd/even translation tables' [patent_app_type] => 1 [patent_app_number] => 8/000246 [patent_app_country] => US [patent_app_date] => 1993-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2874 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/430/05430857.pdf [firstpage_image] =>[orig_patent_app_number] => 000246 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/000246
Method and apparatus for translating logical addresses into physical addresses using odd/even translation tables Jan 3, 1993 Issued
07/999689 DYNAMIC TYPE SEMICONDUCTOR MEMORY DEVICE Dec 30, 1992 Abandoned
Array ( [id] => 3552564 [patent_doc_number] => 05481687 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-02 [patent_title] => 'Method for reducing the number of bits in a binary word representing a series of addresses' [patent_app_type] => 1 [patent_app_number] => 7/995973 [patent_app_country] => US [patent_app_date] => 1992-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7904 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 354 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/481/05481687.pdf [firstpage_image] =>[orig_patent_app_number] => 995973 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/995973
Method for reducing the number of bits in a binary word representing a series of addresses Dec 22, 1992 Issued
Array ( [id] => 3579430 [patent_doc_number] => 05485588 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-16 [patent_title] => 'Memory array based data reorganizer' [patent_app_type] => 1 [patent_app_number] => 7/995400 [patent_app_country] => US [patent_app_date] => 1992-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2340 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/485/05485588.pdf [firstpage_image] =>[orig_patent_app_number] => 995400 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/995400
Memory array based data reorganizer Dec 17, 1992 Issued
Array ( [id] => 3473407 [patent_doc_number] => 05392415 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-21 [patent_title] => 'System for grouping non-contiguous pages belonging to a storage object for page out' [patent_app_type] => 1 [patent_app_number] => 7/991017 [patent_app_country] => US [patent_app_date] => 1992-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4191 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/392/05392415.pdf [firstpage_image] =>[orig_patent_app_number] => 991017 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/991017
System for grouping non-contiguous pages belonging to a storage object for page out Dec 14, 1992 Issued
Array ( [id] => 3454250 [patent_doc_number] => 05430856 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-04 [patent_title] => 'Data processing system simultaneously performing plural translations of virtual addresses having different page sizes' [patent_app_type] => 1 [patent_app_number] => 7/989829 [patent_app_country] => US [patent_app_date] => 1992-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4585 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/430/05430856.pdf [firstpage_image] =>[orig_patent_app_number] => 989829 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/989829
Data processing system simultaneously performing plural translations of virtual addresses having different page sizes Dec 13, 1992 Issued
Array ( [id] => 2915308 [patent_doc_number] => 05249265 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-28 [patent_title] => 'Structure storage management in a graphics display device' [patent_app_type] => 1 [patent_app_number] => 7/987983 [patent_app_country] => US [patent_app_date] => 1992-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 3980 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/249/05249265.pdf [firstpage_image] =>[orig_patent_app_number] => 987983 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/987983
Structure storage management in a graphics display device Dec 8, 1992 Issued
07/978606 SYSTEM FOR DESIGNATING REAL MAIN STORAGE ADDRESSES IN INSTRUCTIONS WHILE DYNAMIC ADDRESS TRANSLATION IS ON Nov 18, 1992 Abandoned
07/976366 COHERENCY FOR WRITE-BACK CACHE IN A SYSTEM DESIGNED FOR WRITE-THROUGH CACHE Nov 12, 1992 Abandoned
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