Application number | Title of the application | Filing Date | Status |
---|
Array
(
[id] => 3015654
[patent_doc_number] => 05371867
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-12-06
[patent_title] => 'Method of using small addresses to access any guest zone in a large memory'
[patent_app_type] => 1
[patent_app_number] => 7/974393
[patent_app_country] => US
[patent_app_date] => 1992-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 8005
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 279
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/371/05371867.pdf
[firstpage_image] =>[orig_patent_app_number] => 974393
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/974393 | Method of using small addresses to access any guest zone in a large memory | Nov 9, 1992 | Issued |
Array
(
[id] => 3474251
[patent_doc_number] => 05469556
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-11-21
[patent_title] => 'Resource access security system for controlling access to resources of a data processing system'
[patent_app_type] => 1
[patent_app_number] => 7/972510
[patent_app_country] => US
[patent_app_date] => 1992-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 6063
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 236
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/469/05469556.pdf
[firstpage_image] =>[orig_patent_app_number] => 972510
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/972510 | Resource access security system for controlling access to resources of a data processing system | Nov 5, 1992 | Issued |
Array
(
[id] => 3526385
[patent_doc_number] => 05513335
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-30
[patent_title] => 'Cache tag memory having first and second single-port arrays and a dual-port array'
[patent_app_type] => 1
[patent_app_number] => 7/970188
[patent_app_country] => US
[patent_app_date] => 1992-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 4
[patent_no_of_words] => 2875
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 271
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/513/05513335.pdf
[firstpage_image] =>[orig_patent_app_number] => 970188
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/970188 | Cache tag memory having first and second single-port arrays and a dual-port array | Nov 1, 1992 | Issued |
07/969536 | DUAL PORT MULTIPLE BLOCK MEMORY CAPABLE OF TIME DIVISIONAL OPERATION | Oct 29, 1992 | Abandoned |
Array
(
[id] => 3128649
[patent_doc_number] => 05410663
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-04-25
[patent_title] => 'Method and system for cache memory congruence class management in a data processing system'
[patent_app_type] => 1
[patent_app_number] => 7/962436
[patent_app_country] => US
[patent_app_date] => 1992-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 3157
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 295
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/410/05410663.pdf
[firstpage_image] =>[orig_patent_app_number] => 962436
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/962436 | Method and system for cache memory congruence class management in a data processing system | Oct 14, 1992 | Issued |
Array
(
[id] => 3432312
[patent_doc_number] => 05479624
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-12-26
[patent_title] => 'High-performance interleaved memory system comprising a prime number of memory modules'
[patent_app_type] => 1
[patent_app_number] => 7/960853
[patent_app_country] => US
[patent_app_date] => 1992-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 19584
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/479/05479624.pdf
[firstpage_image] =>[orig_patent_app_number] => 960853
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/960853 | High-performance interleaved memory system comprising a prime number of memory modules | Oct 13, 1992 | Issued |
07/956469 | RANDOM ACCESS MEMORY WITH DIVIDED MEMORY BANKS AND DATA READ/WRITE ARCHITECTURE THEREFOR | Oct 1, 1992 | Abandoned |
Array
(
[id] => 3500471
[patent_doc_number] => 05475825
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-12-12
[patent_title] => 'Semiconductor device having combined fully associative memories'
[patent_app_type] => 1
[patent_app_number] => 7/952990
[patent_app_country] => US
[patent_app_date] => 1992-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 14
[patent_no_of_words] => 9244
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 530
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/475/05475825.pdf
[firstpage_image] =>[orig_patent_app_number] => 952990
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/952990 | Semiconductor device having combined fully associative memories | Sep 28, 1992 | Issued |
Array
(
[id] => 3532719
[patent_doc_number] => 05490258
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-02-06
[patent_title] => 'Associative memory for very large key spaces'
[patent_app_type] => 1
[patent_app_number] => 7/952988
[patent_app_country] => US
[patent_app_date] => 1992-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 22911
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/490/05490258.pdf
[firstpage_image] =>[orig_patent_app_number] => 952988
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/952988 | Associative memory for very large key spaces | Sep 28, 1992 | Issued |
07/942160 | ONE CLOCK ADDRESS PIPELINING IN SEGMENTATION UNIT | Sep 7, 1992 | Abandoned |
Array
(
[id] => 3600035
[patent_doc_number] => 05497469
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-03-05
[patent_title] => 'Dynamic address translation allowing quick update of the change bit'
[patent_app_type] => 1
[patent_app_number] => 7/939721
[patent_app_country] => US
[patent_app_date] => 1992-09-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 6242
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/497/05497469.pdf
[firstpage_image] =>[orig_patent_app_number] => 939721
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/939721 | Dynamic address translation allowing quick update of the change bit | Sep 1, 1992 | Issued |
Array
(
[id] => 2931437
[patent_doc_number] => 05235543
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-08-10
[patent_title] => 'Dual port static memory with one cycle read-modify-write'
[patent_app_type] => 1
[patent_app_number] => 7/932905
[patent_app_country] => US
[patent_app_date] => 1992-08-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 4049
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 245
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/235/05235543.pdf
[firstpage_image] =>[orig_patent_app_number] => 932905
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/932905 | Dual port static memory with one cycle read-modify-write | Aug 18, 1992 | Issued |
07/921409 | NONVOLATILE MEMORY ELEMENT COMPOSED OF COMBINED SUPERCONDUCTOR RING AND MOSFET | Jul 30, 1992 | Abandoned |
Array
(
[id] => 3007354
[patent_doc_number] => 05367650
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-11-22
[patent_title] => 'Method and apparauts for parallel exchange operation in a pipelined processor'
[patent_app_type] => 1
[patent_app_number] => 7/923148
[patent_app_country] => US
[patent_app_date] => 1992-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 8896
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 285
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/367/05367650.pdf
[firstpage_image] =>[orig_patent_app_number] => 923148
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/923148 | Method and apparauts for parallel exchange operation in a pipelined processor | Jul 30, 1992 | Issued |
Array
(
[id] => 3041815
[patent_doc_number] => 05317715
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-05-31
[patent_title] => 'Reduced instruction set computer system including apparatus and method for coupling a high performance RISC interface to a peripheral bus having different performance characteristics'
[patent_app_type] => 1
[patent_app_number] => 7/911783
[patent_app_country] => US
[patent_app_date] => 1992-07-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 23847
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 343
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/317/05317715.pdf
[firstpage_image] =>[orig_patent_app_number] => 911783
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/911783 | Reduced instruction set computer system including apparatus and method for coupling a high performance RISC interface to a peripheral bus having different performance characteristics | Jul 9, 1992 | Issued |
Array
(
[id] => 3138519
[patent_doc_number] => 05437016
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-07-25
[patent_title] => 'Apparatus and method for translating logical addresses for virtual machines'
[patent_app_type] => 1
[patent_app_number] => 7/909308
[patent_app_country] => US
[patent_app_date] => 1992-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 5267
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 199
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/437/05437016.pdf
[firstpage_image] =>[orig_patent_app_number] => 909308
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/909308 | Apparatus and method for translating logical addresses for virtual machines | Jul 5, 1992 | Issued |
Array
(
[id] => 3420053
[patent_doc_number] => 05438666
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-08-01
[patent_title] => 'Shared memory bus system for arbitrating access control among contending memory refresh circuits, peripheral controllers, and bus masters'
[patent_app_type] => 1
[patent_app_number] => 7/908441
[patent_app_country] => US
[patent_app_date] => 1992-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 16
[patent_no_of_words] => 17459
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 233
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/438/05438666.pdf
[firstpage_image] =>[orig_patent_app_number] => 908441
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/908441 | Shared memory bus system for arbitrating access control among contending memory refresh circuits, peripheral controllers, and bus masters | Jun 29, 1992 | Issued |
Array
(
[id] => 3502635
[patent_doc_number] => 05440708
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-08-08
[patent_title] => 'Microprocessor and storage management system having said microprocessor'
[patent_app_type] => 1
[patent_app_number] => 7/906967
[patent_app_country] => US
[patent_app_date] => 1992-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 16
[patent_no_of_words] => 10780
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 217
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/440/05440708.pdf
[firstpage_image] =>[orig_patent_app_number] => 906967
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/906967 | Microprocessor and storage management system having said microprocessor | Jun 29, 1992 | Issued |
Array
(
[id] => 3075128
[patent_doc_number] => 05295096
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-03-15
[patent_title] => 'NAND type EEPROM and operating method therefor'
[patent_app_type] => 1
[patent_app_number] => 7/905191
[patent_app_country] => US
[patent_app_date] => 1992-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 29
[patent_no_of_words] => 8552
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 276
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/295/05295096.pdf
[firstpage_image] =>[orig_patent_app_number] => 905191
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/905191 | NAND type EEPROM and operating method therefor | Jun 25, 1992 | Issued |
Array
(
[id] => 3015639
[patent_doc_number] => 05371866
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-12-06
[patent_title] => 'Simulcast standard multichip memory addressing system'
[patent_app_type] => 1
[patent_app_number] => 7/891609
[patent_app_country] => US
[patent_app_date] => 1992-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2838
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 179
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/371/05371866.pdf
[firstpage_image] =>[orig_patent_app_number] => 891609
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/891609 | Simulcast standard multichip memory addressing system | May 31, 1992 | Issued |