Derrick Edward Holland

Array ( [id] => 2969753 [patent_doc_number] => 05198994 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-30 [patent_title] => 'Ferroelectric memory device' [patent_app_type] => 1 [patent_app_number] => 7/789538 [patent_app_country] => US [patent_app_date] => 1991-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 22 [patent_no_of_words] => 4650 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/198/05198994.pdf [firstpage_image] =>[orig_patent_app_number] => 789538 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3099407 [patent_doc_number] => 05278786 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-11 [patent_title] => 'Non-volatile semiconductor memory device having an area responsive to writing allowance signal' [patent_app_type] => 1 [patent_app_number] => 7/771832 [patent_app_country] => US [patent_app_date] => 1991-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4017 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/278/05278786.pdf [firstpage_image] =>[orig_patent_app_number] => 771832 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3021135 [patent_doc_number] => 05355462 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-11 [patent_title] => 'Processor data memory address generator' [patent_app_type] => 1 [patent_app_number] => 7/762821 [patent_app_country] => US [patent_app_date] => 1991-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4044 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/355/05355462.pdf [firstpage_image] =>[orig_patent_app_number] => 762821 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2931658 [patent_doc_number] => 05200920 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-06 [patent_title] => 'Method for programming programmable elements in programmable devices' [patent_app_type] => 1 [patent_app_number] => 7/759944 [patent_app_country] => US [patent_app_date] => 1991-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4078 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/200/05200920.pdf [firstpage_image] =>[orig_patent_app_number] => 759944 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2973805 [patent_doc_number] => 05265056 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-23 [patent_title] => 'Signal margin testing system for dynamic RAM' [patent_app_type] => 1 [patent_app_number] => 7/764103 [patent_app_country] => US [patent_app_date] => 1991-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4513 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/265/05265056.pdf [firstpage_image] =>[orig_patent_app_number] => 764103 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2943933 [patent_doc_number] => 05189640 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-02-23 [patent_title] => 'High speed, multi-port memory cell utilizable in a BICMOS memory array' [patent_app_type] => 1 [patent_app_number] => 7/758226 [patent_app_country] => US [patent_app_date] => 1991-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2789 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/189/05189640.pdf [firstpage_image] =>[orig_patent_app_number] => 758226 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3456746 [patent_doc_number] => 05388240 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-07 [patent_title] => 'DRAM chip and decoding arrangement and method for cache fills' [patent_app_type] => 1 [patent_app_number] => 7/751495 [patent_app_country] => US [patent_app_date] => 1991-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2270 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 372 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/388/05388240.pdf [firstpage_image] =>[orig_patent_app_number] => 751495 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2813447 [patent_doc_number] => 05124948 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-23 [patent_title] => 'Mask ROM with spare memory cells' [patent_app_type] => 1 [patent_app_number] => 7/751574 [patent_app_country] => US [patent_app_date] => 1991-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7448 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 378 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/124/05124948.pdf [firstpage_image] =>[orig_patent_app_number] => 751574 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2989390 [patent_doc_number] => 05204838 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-20 [patent_title] => 'High speed readout circuit' [patent_app_type] => 1 [patent_app_number] => 7/751618 [patent_app_country] => US [patent_app_date] => 1991-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3343 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/204/05204838.pdf [firstpage_image] =>[orig_patent_app_number] => 751618 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3020494 [patent_doc_number] => 05276649 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-04 [patent_title] => 'Dynamic-type semiconductor memory device having staggered activation of column groups' [patent_app_type] => 1 [patent_app_number] => 7/746092 [patent_app_country] => US [patent_app_date] => 1991-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 25 [patent_no_of_words] => 10474 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/276/05276649.pdf [firstpage_image] =>[orig_patent_app_number] => 746092 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3106630 [patent_doc_number] => 05369750 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-29 [patent_title] => 'Method and apparatus for configuring multiple absolute address spaces' [patent_app_type] => 1 [patent_app_number] => 7/743754 [patent_app_country] => US [patent_app_date] => 1991-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 6300 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/369/05369750.pdf [firstpage_image] =>[orig_patent_app_number] => 743754 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3110384 [patent_doc_number] => 05293597 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-08 [patent_title] => 'Concurrent context memory management unit' [patent_app_type] => 1 [patent_app_number] => 7/737961 [patent_app_country] => US [patent_app_date] => 1991-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2619 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/293/05293597.pdf [firstpage_image] =>[orig_patent_app_number] => 737961 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3433329 [patent_doc_number] => 05390309 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-14 [patent_title] => 'Virtual address translation in three level virtual machine' [patent_app_type] => 1 [patent_app_number] => 7/736022 [patent_app_country] => US [patent_app_date] => 1991-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 10153 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/390/05390309.pdf [firstpage_image] =>[orig_patent_app_number] => 736022 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3502608 [patent_doc_number] => 05440706 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-08 [patent_title] => 'Data shuffling apparatus possessing reduced memory' [patent_app_type] => 1 [patent_app_number] => 7/733211 [patent_app_country] => US [patent_app_date] => 1991-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4114 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/440/05440706.pdf [firstpage_image] =>[orig_patent_app_number] => 733211 [rel_patent_id] =>[rel_patent_doc_number] =>)