Search

Derrick Edward Holland

Examiner (ID: 404, Phone: (571)272-3089 , Office: P/2912 )

Most Active Art Unit
2912
Art Unit(s)
2912
Total Applications
3302
Issued Applications
3253
Pending Applications
21
Abandoned Applications
28

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3110349 [patent_doc_number] => 05293595 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-08 [patent_title] => 'Paging system using extension tables for conflict resolution' [patent_app_type] => 1 [patent_app_number] => 7/628056 [patent_app_country] => US [patent_app_date] => 1990-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4318 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 376 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/293/05293595.pdf [firstpage_image] =>[orig_patent_app_number] => 628056 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/628056
Paging system using extension tables for conflict resolution Dec 16, 1990 Issued
07/617930 DYNAMIC SEMICONDUCTOR MEMORY DEVICE HAVING HIGH-SPEED ACCESS Nov 25, 1990 Abandoned
07/614082 SHARED MEMORY BUS SYSTEM FOR ARBITRATING ACCESS CONTROL AMONG CONTENDING MEMORY REFRESH CIRCUITS, PERIPHERAL CONTROLLERS, AND BUS MASTERS Nov 12, 1990 Abandoned
Array ( [id] => 2945332 [patent_doc_number] => 05233700 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-03 [patent_title] => 'Address translation device with an address translation buffer loaded with presence bits' [patent_app_type] => 1 [patent_app_number] => 7/605458 [patent_app_country] => US [patent_app_date] => 1990-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4852 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 406 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/233/05233700.pdf [firstpage_image] =>[orig_patent_app_number] => 605458 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/605458
Address translation device with an address translation buffer loaded with presence bits Oct 29, 1990 Issued
Array ( [id] => 3070206 [patent_doc_number] => 05339397 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-16 [patent_title] => 'Hardware primary directory lock' [patent_app_type] => 1 [patent_app_number] => 7/596812 [patent_app_country] => US [patent_app_date] => 1990-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 6841 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 381 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/339/05339397.pdf [firstpage_image] =>[orig_patent_app_number] => 596812 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/596812
Hardware primary directory lock Oct 11, 1990 Issued
Array ( [id] => 2843810 [patent_doc_number] => 05129070 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-07 [patent_title] => 'Method of using the memory in an information processing system of the virtual addressing type, and apparatus for performing the method' [patent_app_type] => 1 [patent_app_number] => 7/592036 [patent_app_country] => US [patent_app_date] => 1990-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 11019 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/129/05129070.pdf [firstpage_image] =>[orig_patent_app_number] => 592036 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/592036
Method of using the memory in an information processing system of the virtual addressing type, and apparatus for performing the method Oct 2, 1990 Issued
07/593540 REDUCED INSTRUCTION SET COMPUTER SYSTEM INCLUDING APPARATUS AND METHOD FOR COUPLING A HIGH PERFORMANCE RISC INTERFACE TO A PERIPHERAL BUS HAVING DIFFERENT PERFORMANCE CHARACTERISTICS Oct 2, 1990 Abandoned
07/586914 MULTIFUNCTIONAL ACCESS DEVICES, SYSTEMS AND METHODS Sep 23, 1990 Abandoned
Array ( [id] => 3077983 [patent_doc_number] => 05295251 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-15 [patent_title] => 'Method of accessing multiple virtual address spaces and computer system' [patent_app_type] => 1 [patent_app_number] => 7/585973 [patent_app_country] => US [patent_app_date] => 1990-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3768 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/295/05295251.pdf [firstpage_image] =>[orig_patent_app_number] => 585973 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/585973
Method of accessing multiple virtual address spaces and computer system Sep 20, 1990 Issued
07/580352 REDUNDANT CIRCUIT FOR MEMORY CELL BLOCKS Sep 6, 1990 Abandoned
07/578699 SERIAL ARCHITECTURE FOR MEMORY MODULE CONTROL Sep 3, 1990 Abandoned
07/574162 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DATA TRANSFER THEREFOR Aug 28, 1990 Abandoned
Array ( [id] => 3038327 [patent_doc_number] => 05317533 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-31 [patent_title] => 'Integrated mass storage device' [patent_app_type] => 1 [patent_app_number] => 7/566335 [patent_app_country] => US [patent_app_date] => 1990-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 46 [patent_no_of_words] => 13837 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/317/05317533.pdf [firstpage_image] =>[orig_patent_app_number] => 566335 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/566335
Integrated mass storage device Aug 16, 1990 Issued
Array ( [id] => 4014634 [patent_doc_number] => 05923864 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Virtual storage address space access control system including auxiliary translation lookaside buffer' [patent_app_type] => 1 [patent_app_number] => 7/557707 [patent_app_country] => US [patent_app_date] => 1990-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5722 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/923/05923864.pdf [firstpage_image] =>[orig_patent_app_number] => 557707 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/557707
Virtual storage address space access control system including auxiliary translation lookaside buffer Jul 24, 1990 Issued
Array ( [id] => 2922254 [patent_doc_number] => 05227995 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-13 [patent_title] => 'High density semiconductor memory module using split finger lead frame' [patent_app_type] => 1 [patent_app_number] => 7/554635 [patent_app_country] => US [patent_app_date] => 1990-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1454 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/227/05227995.pdf [firstpage_image] =>[orig_patent_app_number] => 554635 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/554635
High density semiconductor memory module using split finger lead frame Jul 16, 1990 Issued
Array ( [id] => 2775878 [patent_doc_number] => 05007028 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-04-09 [patent_title] => 'Multiport memory with improved timing of word line selection' [patent_app_type] => 1 [patent_app_number] => 7/552851 [patent_app_country] => US [patent_app_date] => 1990-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 2066 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/007/05007028.pdf [firstpage_image] =>[orig_patent_app_number] => 552851 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/552851
Multiport memory with improved timing of word line selection Jul 15, 1990 Issued
Array ( [id] => 2931529 [patent_doc_number] => 05235548 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-10 [patent_title] => 'Memory with power supply intercept in redundancy logic' [patent_app_type] => 1 [patent_app_number] => 7/554978 [patent_app_country] => US [patent_app_date] => 1990-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4152 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 350 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/235/05235548.pdf [firstpage_image] =>[orig_patent_app_number] => 554978 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/554978
Memory with power supply intercept in redundancy logic Jul 11, 1990 Issued
Array ( [id] => 3105065 [patent_doc_number] => 05291434 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-01 [patent_title] => 'MOS fuse with oxide breakdown and application thereof to memory cards' [patent_app_type] => 1 [patent_app_number] => 7/551565 [patent_app_country] => US [patent_app_date] => 1990-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 6 [patent_no_of_words] => 2862 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/291/05291434.pdf [firstpage_image] =>[orig_patent_app_number] => 551565 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/551565
MOS fuse with oxide breakdown and application thereof to memory cards Jul 10, 1990 Issued
Array ( [id] => 2927852 [patent_doc_number] => 05179689 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-01-12 [patent_title] => 'Dataprocessing device with instruction cache' [patent_app_type] => 1 [patent_app_number] => 7/550231 [patent_app_country] => US [patent_app_date] => 1990-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 20703 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/179/05179689.pdf [firstpage_image] =>[orig_patent_app_number] => 550231 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/550231
Dataprocessing device with instruction cache Jul 9, 1990 Issued
07/546395 BIPOLAR TRANSISTOR MEMORY CELL AND METHOD Jun 28, 1990 Abandoned
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