Search

Derrick V. Rose

Examiner (ID: 2179, Phone: (571)270-7460 , Office: P/2462 )

Most Active Art Unit
2462
Art Unit(s)
2462
Total Applications
616
Issued Applications
482
Pending Applications
56
Abandoned Applications
87

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20103573 [patent_doc_number] => 20250233509 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-17 [patent_title] => METHOD AND CONTROL CIRCUIT FOR OPERATING A HALF-BRIDGE CIRCUIT [patent_app_type] => utility [patent_app_number] => 19/013033 [patent_app_country] => US [patent_app_date] => 2025-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3482 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19013033 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/013033
METHOD AND CONTROL CIRCUIT FOR OPERATING A HALF-BRIDGE CIRCUIT Jan 7, 2025 Pending
Array ( [id] => 19987500 [patent_doc_number] => 20250125722 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-17 [patent_title] => PUMPING CONTROLLER FOR A PLURALITY OF CHARGE PUMP UNITS [patent_app_type] => utility [patent_app_number] => 18/988877 [patent_app_country] => US [patent_app_date] => 2024-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 883 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18988877 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/988877
PUMPING CONTROLLER FOR A PLURALITY OF CHARGE PUMP UNITS Dec 18, 2024 Pending
Array ( [id] => 20064243 [patent_doc_number] => 20250202465 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => Systems, Methods, and Devices of Tri-State Inverters [patent_app_type] => utility [patent_app_number] => 18/985249 [patent_app_country] => US [patent_app_date] => 2024-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5736 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18985249 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/985249
Systems, Methods, and Devices of Tri-State Inverters Dec 17, 2024 Pending
Array ( [id] => 19851430 [patent_doc_number] => 20250096781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => SEMICONDUCTOR SWITCH DRIVE CIRCUIT WITH TRANSFER RESTRICTING CIRCUITRY [patent_app_type] => utility [patent_app_number] => 18/969294 [patent_app_country] => US [patent_app_date] => 2024-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17813 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18969294 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/969294
SEMICONDUCTOR SWITCH DRIVE CIRCUIT WITH TRANSFER RESTRICTING CIRCUITRY Dec 4, 2024 Pending
Array ( [id] => 20020390 [patent_doc_number] => 20250158612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => INPUT BUFFERING GATE-TO-SOURCE (VGS) VOLTAGE OF A SILICON CARBIDE (SIC) FIELD-EFFECT TRANSISTOR (FET) [patent_app_type] => utility [patent_app_number] => 18/949712 [patent_app_country] => US [patent_app_date] => 2024-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1100 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18949712 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/949712
INPUT BUFFERING GATE-TO-SOURCE (VGS) VOLTAGE OF A SILICON CARBIDE (SIC) FIELD-EFFECT TRANSISTOR (FET) Nov 14, 2024 Pending
Array ( [id] => 20034737 [patent_doc_number] => 20250172959 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => VOLTAGE REGULATOR AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/907597 [patent_app_country] => US [patent_app_date] => 2024-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18907597 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/907597
Voltage regulator and semiconductor device Oct 6, 2024 Issued
Array ( [id] => 20029568 [patent_doc_number] => 20250167790 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-22 [patent_title] => APPARATUS AND METHOD FOR GENERATING CLOCK TO INCREASE POWER EFFICIENCY [patent_app_type] => utility [patent_app_number] => 18/889081 [patent_app_country] => US [patent_app_date] => 2024-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14225 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18889081 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/889081
APPARATUS AND METHOD FOR GENERATING CLOCK TO INCREASE POWER EFFICIENCY Sep 17, 2024 Pending
Array ( [id] => 19851448 [patent_doc_number] => 20250096799 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => PROTECTION STRUCTURE FOR AN ENHANCEMENT-MODE FET OF A CIRCUIT AND CORRESPONDING METHOD [patent_app_type] => utility [patent_app_number] => 18/819313 [patent_app_country] => US [patent_app_date] => 2024-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8222 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18819313 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/819313
PROTECTION STRUCTURE FOR AN ENHANCEMENT-MODE FET OF A CIRCUIT AND CORRESPONDING METHOD Aug 28, 2024 Pending
Array ( [id] => 20521833 [patent_doc_number] => 20260045942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-12 [patent_title] => LATCH COMPARATOR [patent_app_type] => utility [patent_app_number] => 18/798277 [patent_app_country] => US [patent_app_date] => 2024-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2430 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18798277 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/798277
LATCH COMPARATOR Aug 7, 2024 Pending
Array ( [id] => 20521843 [patent_doc_number] => 20260045952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-12 [patent_title] => OUTPUT SWITCHING SIGNAL USING CAPACITIVE ELEMENT DISCHARGING [patent_app_type] => utility [patent_app_number] => 18/797108 [patent_app_country] => US [patent_app_date] => 2024-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2576 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18797108 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/797108
OUTPUT SWITCHING SIGNAL USING CAPACITIVE ELEMENT DISCHARGING Aug 6, 2024 Pending
Array ( [id] => 20502332 [patent_doc_number] => 20260031795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-29 [patent_title] => TUNABLE RESISTOR CIRCUITS [patent_app_type] => utility [patent_app_number] => 18/784671 [patent_app_country] => US [patent_app_date] => 2024-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1151 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18784671 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/784671
Tunable resistor circuits Jul 24, 2024 Issued
Array ( [id] => 19697251 [patent_doc_number] => 20250015796 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => DETECTION OF LEAKAGE CURRENTS IN INTELLIGENT SEMICONDUCTOR SWITCH [patent_app_type] => utility [patent_app_number] => 18/763431 [patent_app_country] => US [patent_app_date] => 2024-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5302 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18763431 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/763431
DETECTION OF LEAKAGE CURRENTS IN INTELLIGENT SEMICONDUCTOR SWITCH Jul 2, 2024 Pending
Array ( [id] => 20265516 [patent_doc_number] => 12436504 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Using time-to-digital converters to delay signals with high accuracy and large range [patent_app_type] => utility [patent_app_number] => 18/673897 [patent_app_country] => US [patent_app_date] => 2024-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 0 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18673897 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/673897
Using time-to-digital converters to delay signals with high accuracy and large range May 23, 2024 Issued
Array ( [id] => 20325314 [patent_doc_number] => 20250337402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-30 [patent_title] => GATE DRIVE CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/663108 [patent_app_country] => US [patent_app_date] => 2024-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18663108 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/663108
Gate drive circuit May 13, 2024 Issued
Array ( [id] => 19750172 [patent_doc_number] => 20250038737 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/659670 [patent_app_country] => US [patent_app_date] => 2024-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6529 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18659670 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/659670
SEMICONDUCTOR DEVICE May 8, 2024 Pending
Array ( [id] => 20495650 [patent_doc_number] => 12537532 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-27 [patent_title] => Charge injection reduction in a fractional-N frequency synthesizer [patent_app_type] => utility [patent_app_number] => 18/657260 [patent_app_country] => US [patent_app_date] => 2024-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 2776 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18657260 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/657260
Charge injection reduction in a fractional-N frequency synthesizer May 6, 2024 Issued
Array ( [id] => 20197402 [patent_doc_number] => 20250274112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-28 [patent_title] => CLOCK SIGNAL DUTY RATIO CORRECTION CIRCUIT AND METHOD OF CORRECTING DUTY RATIO [patent_app_type] => utility [patent_app_number] => 18/656733 [patent_app_country] => US [patent_app_date] => 2024-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18656733 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/656733
CLOCK SIGNAL DUTY RATIO CORRECTION CIRCUIT AND METHOD OF CORRECTING DUTY RATIO May 6, 2024 Pending
Array ( [id] => 20353433 [patent_doc_number] => 20250350285 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-13 [patent_title] => NOISE DOWN CONVERSION FOR JITTER REDUCTION [patent_app_type] => utility [patent_app_number] => 18/657069 [patent_app_country] => US [patent_app_date] => 2024-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18657069 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/657069
NOISE DOWN CONVERSION FOR JITTER REDUCTION May 6, 2024 Pending
Array ( [id] => 20339431 [patent_doc_number] => 20250343551 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-06 [patent_title] => DELAY LINE TEMPERATURE CALIBRATION [patent_app_type] => utility [patent_app_number] => 18/656442 [patent_app_country] => US [patent_app_date] => 2024-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7792 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18656442 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/656442
Delay line temperature calibration May 5, 2024 Issued
Array ( [id] => 19590721 [patent_doc_number] => 20240388278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => NODE VOLTAGE CONTROL [patent_app_type] => utility [patent_app_number] => 18/653140 [patent_app_country] => US [patent_app_date] => 2024-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5941 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18653140 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/653140
NODE VOLTAGE CONTROL May 1, 2024 Pending
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