Search

Derris Holt Banks

Director (ID: 19179, Phone: (571)272-5860 , Office: P/2600 )

Most Active Art Unit
3723
Art Unit(s)
2600, 3725, 3203, 3712, 3723, 3729, 2899, DCIPC
Total Applications
859
Issued Applications
701
Pending Applications
111
Abandoned Applications
47

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6794804 [patent_doc_number] => 20030173677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-18 [patent_title] => 'Semiconductor device having a capacitor and method for the manufacture thereof' [patent_app_type] => new [patent_app_number] => 10/412256 [patent_app_country] => US [patent_app_date] => 2003-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2562 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20030173677.pdf [firstpage_image] =>[orig_patent_app_number] => 10412256 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/412256
Semiconductor device having a capacitor and method for the manufacture thereof Apr 13, 2003 Abandoned
Array ( [id] => 6797161 [patent_doc_number] => 20030176035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-18 [patent_title] => 'Analog capacitor in dual damascene process' [patent_app_type] => new [patent_app_number] => 10/409499 [patent_app_country] => US [patent_app_date] => 2003-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3474 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0176/20030176035.pdf [firstpage_image] =>[orig_patent_app_number] => 10409499 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/409499
Analog capacitor in dual damascene process Apr 7, 2003 Issued
Array ( [id] => 7462799 [patent_doc_number] => 20040198060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-07 [patent_title] => 'Selective spacer layer deposition method for forming spacers with different widths' [patent_app_type] => new [patent_app_number] => 10/408689 [patent_app_country] => US [patent_app_date] => 2003-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2128 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20040198060.pdf [firstpage_image] =>[orig_patent_app_number] => 10408689 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/408689
Selective spacer layer deposition method for forming spacers with different widths Apr 6, 2003 Issued
Array ( [id] => 7441900 [patent_doc_number] => 20040195650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-07 [patent_title] => 'High-Q inductor device with a shielding pattern embedded in a substrate' [patent_app_type] => new [patent_app_number] => 10/406939 [patent_app_country] => US [patent_app_date] => 2003-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2952 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20040195650.pdf [firstpage_image] =>[orig_patent_app_number] => 10406939 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/406939
High-Q inductor device with a shielding pattern embedded in a substrate Apr 3, 2003 Abandoned
Array ( [id] => 6701681 [patent_doc_number] => 20030224561 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-04 [patent_title] => 'Top gate thin-film transistor and method of producing the same' [patent_app_type] => new [patent_app_number] => 10/407085 [patent_app_country] => US [patent_app_date] => 2003-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4652 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0224/20030224561.pdf [firstpage_image] =>[orig_patent_app_number] => 10407085 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/407085
Top gate thin-film transistor and method of producing the same Apr 3, 2003 Abandoned
Array ( [id] => 7442291 [patent_doc_number] => 20040195688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-07 [patent_title] => 'Custom electrodes for molecular memory and logic devices' [patent_app_type] => new [patent_app_number] => 10/405294 [patent_app_country] => US [patent_app_date] => 2003-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 8209 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20040195688.pdf [firstpage_image] =>[orig_patent_app_number] => 10405294 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/405294
Custom electrodes for molecular memory and logic devices Apr 1, 2003 Issued
Array ( [id] => 638357 [patent_doc_number] => 07126210 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-24 [patent_title] => 'System and method for venting pressure from an integrated circuit package sealed with a lid' [patent_app_type] => utility [patent_app_number] => 10/405529 [patent_app_country] => US [patent_app_date] => 2003-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5443 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/126/07126210.pdf [firstpage_image] =>[orig_patent_app_number] => 10405529 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/405529
System and method for venting pressure from an integrated circuit package sealed with a lid Apr 1, 2003 Issued
Array ( [id] => 6727741 [patent_doc_number] => 20030183931 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-02 [patent_title] => 'Semiconductor apparatus, fixture for measuring characteristics therefor, and semiconductor device characteristics measuring apparatus' [patent_app_type] => new [patent_app_number] => 10/395689 [patent_app_country] => US [patent_app_date] => 2003-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4237 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 17 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0183/20030183931.pdf [firstpage_image] =>[orig_patent_app_number] => 10395689 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/395689
Semiconductor apparatus, fixture for measuring characteristics therefor, and semiconductor device characteristics measuring apparatus Mar 23, 2003 Abandoned
Array ( [id] => 7420788 [patent_doc_number] => 20040183114 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-23 [patent_title] => 'Triple-well charge pump stage with no threshold voltage back-bias effect' [patent_app_type] => new [patent_app_number] => 10/393958 [patent_app_country] => US [patent_app_date] => 2003-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5420 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0183/20040183114.pdf [firstpage_image] =>[orig_patent_app_number] => 10393958 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/393958
Triple-well charge pump stage with no threshold voltage back-bias effect Mar 19, 2003 Issued
Array ( [id] => 1209279 [patent_doc_number] => 06713345 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-30 [patent_title] => 'Semiconductor memory device having a trench and a gate electrode vertically formed on a wall of the trench' [patent_app_type] => B1 [patent_app_number] => 10/390888 [patent_app_country] => US [patent_app_date] => 2003-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 40 [patent_no_of_words] => 9053 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/713/06713345.pdf [firstpage_image] =>[orig_patent_app_number] => 10390888 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/390888
Semiconductor memory device having a trench and a gate electrode vertically formed on a wall of the trench Mar 18, 2003 Issued
Array ( [id] => 6708945 [patent_doc_number] => 20030168694 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-11 [patent_title] => 'Non-volatile memory cells, high voltage transistors and logic transistors integrated on a single chip' [patent_app_type] => new [patent_app_number] => 10/390946 [patent_app_country] => US [patent_app_date] => 2003-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3280 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20030168694.pdf [firstpage_image] =>[orig_patent_app_number] => 10390946 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/390946
Non-volatile memory cells, high voltage transistors and logic transistors integrated on a single chip Mar 17, 2003 Issued
Array ( [id] => 6827596 [patent_doc_number] => 20030178654 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-25 [patent_title] => 'Complementary Schottky junction transistors and methods of forming the same' [patent_app_type] => new [patent_app_number] => 10/391402 [patent_app_country] => US [patent_app_date] => 2003-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8820 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0178/20030178654.pdf [firstpage_image] =>[orig_patent_app_number] => 10391402 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/391402
Complementary Schottky junction transistors and methods of forming the same Mar 16, 2003 Issued
Array ( [id] => 963639 [patent_doc_number] => 06949451 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-27 [patent_title] => 'SOI chip with recess-resistant buried insulator and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 10/384859 [patent_app_country] => US [patent_app_date] => 2003-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 25 [patent_no_of_words] => 5841 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/949/06949451.pdf [firstpage_image] =>[orig_patent_app_number] => 10384859 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/384859
SOI chip with recess-resistant buried insulator and method of manufacturing the same Mar 9, 2003 Issued
Array ( [id] => 1050591 [patent_doc_number] => 06861708 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-01 [patent_title] => 'Semiconductor memory device having a low potential body section' [patent_app_type] => utility [patent_app_number] => 10/383578 [patent_app_country] => US [patent_app_date] => 2003-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 30 [patent_no_of_words] => 5003 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/861/06861708.pdf [firstpage_image] =>[orig_patent_app_number] => 10383578 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/383578
Semiconductor memory device having a low potential body section Mar 9, 2003 Issued
Array ( [id] => 7406812 [patent_doc_number] => 20040175926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-09 [patent_title] => 'METHOD FOR MANUFACTURING A SEMICONDUCTOR COMPONENT HAVING A BARRIER-LINED OPENING' [patent_app_type] => new [patent_app_number] => 10/383318 [patent_app_country] => US [patent_app_date] => 2003-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4285 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20040175926.pdf [firstpage_image] =>[orig_patent_app_number] => 10383318 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/383318
METHOD FOR MANUFACTURING A SEMICONDUCTOR COMPONENT HAVING A BARRIER-LINED OPENING Mar 6, 2003 Abandoned
Array ( [id] => 1080489 [patent_doc_number] => 06835647 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-28 [patent_title] => 'Semiconductor device including a plurality of interconnection layers, manufacturing method thereof and method of designing semiconductor circuit used in the manufacturing method' [patent_app_type] => B2 [patent_app_number] => 10/382902 [patent_app_country] => US [patent_app_date] => 2003-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 11613 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/835/06835647.pdf [firstpage_image] =>[orig_patent_app_number] => 10382902 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/382902
Semiconductor device including a plurality of interconnection layers, manufacturing method thereof and method of designing semiconductor circuit used in the manufacturing method Mar 6, 2003 Issued
Array ( [id] => 7406757 [patent_doc_number] => 20040175918 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-09 [patent_title] => 'Novel formation of an aluminum contact pad free of plasma induced damage by applying CMP' [patent_app_type] => new [patent_app_number] => 10/379818 [patent_app_country] => US [patent_app_date] => 2003-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2543 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20040175918.pdf [firstpage_image] =>[orig_patent_app_number] => 10379818 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/379818
Novel formation of an aluminum contact pad free of plasma induced damage by applying CMP Mar 4, 2003 Abandoned
Array ( [id] => 6794803 [patent_doc_number] => 20030173676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-18 [patent_title] => 'Multi-layered semiconductor device and method of manufacturing same' [patent_app_type] => new [patent_app_number] => 10/375018 [patent_app_country] => US [patent_app_date] => 2003-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6231 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20030173676.pdf [firstpage_image] =>[orig_patent_app_number] => 10375018 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/375018
Multi-layered semiconductor device and method of manufacturing same Feb 27, 2003 Abandoned
Array ( [id] => 7144060 [patent_doc_number] => 20040169281 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-02 [patent_title] => 'Ultra low k plasma CVD nanotube/spin-on dielectrics with improved properties for advanced nanoelectronic device fabrication' [patent_app_type] => new [patent_app_number] => 10/376088 [patent_app_country] => US [patent_app_date] => 2003-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3545 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0169/20040169281.pdf [firstpage_image] =>[orig_patent_app_number] => 10376088 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/376088
Ultra low k plasma CVD nanotube/spin-on dielectrics with improved properties for advanced nanoelectronic device fabrication Feb 26, 2003 Issued
Array ( [id] => 6832783 [patent_doc_number] => 20030160328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-28 [patent_title] => 'Wiring structure in a semiconductor device' [patent_app_type] => new [patent_app_number] => 10/372089 [patent_app_country] => US [patent_app_date] => 2003-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 10033 [patent_no_of_claims] => 58 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20030160328.pdf [firstpage_image] =>[orig_patent_app_number] => 10372089 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/372089
Wiring structure in a semiconductor device Feb 24, 2003 Issued
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