Search

Devan A. Sandiford

Examiner (ID: 4291, Phone: (571)270-7989 , Office: P/2648 )

Most Active Art Unit
2648
Art Unit(s)
4185, 2648, 2618
Total Applications
456
Issued Applications
376
Pending Applications
0
Abandoned Applications
78

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 65045 [patent_doc_number] => 07759779 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-20 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 12/104516 [patent_app_country] => US [patent_app_date] => 2008-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 2821 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/759/07759779.pdf [firstpage_image] =>[orig_patent_app_number] => 12104516 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/104516
Semiconductor device and method of manufacturing the same Apr 16, 2008 Issued
Array ( [id] => 4839935 [patent_doc_number] => 20080280421 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-13 [patent_title] => 'WAFER DIVIDING METHOD' [patent_app_type] => utility [patent_app_number] => 12/105020 [patent_app_country] => US [patent_app_date] => 2008-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6498 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0280/20080280421.pdf [firstpage_image] =>[orig_patent_app_number] => 12105020 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/105020
WAFER DIVIDING METHOD Apr 16, 2008 Abandoned
Array ( [id] => 5458335 [patent_doc_number] => 20090258487 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-15 [patent_title] => 'Method for Improving the Reliability of Low-k Dielectric Materials' [patent_app_type] => utility [patent_app_number] => 12/102695 [patent_app_country] => US [patent_app_date] => 2008-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3827 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0258/20090258487.pdf [firstpage_image] =>[orig_patent_app_number] => 12102695 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/102695
Method for Improving the Reliability of Low-k Dielectric Materials Apr 13, 2008 Abandoned
Array ( [id] => 4663650 [patent_doc_number] => 20080254557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-16 [patent_title] => 'Method for manufacturing lens for led package' [patent_app_type] => utility [patent_app_number] => 12/081066 [patent_app_country] => US [patent_app_date] => 2008-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2909 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0254/20080254557.pdf [firstpage_image] =>[orig_patent_app_number] => 12081066 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/081066
Method for manufacturing lens for led package Apr 9, 2008 Abandoned
Array ( [id] => 5319676 [patent_doc_number] => 20090057666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-05 [patent_title] => 'PIXEL STRUCTURE AND FABRICATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/055326 [patent_app_country] => US [patent_app_date] => 2008-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6383 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20090057666.pdf [firstpage_image] =>[orig_patent_app_number] => 12055326 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/055326
Pixel structure and fabricating method thereof Mar 25, 2008 Issued
Array ( [id] => 159198 [patent_doc_number] => 07674688 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-09 [patent_title] => 'Sawing method for a semiconductor element with a microelectromechanical system' [patent_app_type] => utility [patent_app_number] => 12/051896 [patent_app_country] => US [patent_app_date] => 2008-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 24 [patent_no_of_words] => 2590 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/674/07674688.pdf [firstpage_image] =>[orig_patent_app_number] => 12051896 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/051896
Sawing method for a semiconductor element with a microelectromechanical system Mar 19, 2008 Issued
Array ( [id] => 5435718 [patent_doc_number] => 20090170305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'METHOD FOR IMPROVING ELECTROMIGRATION LIFETIME FOR CU INTERCONNECT SYSTEMS' [patent_app_type] => utility [patent_app_number] => 12/047485 [patent_app_country] => US [patent_app_date] => 2008-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3054 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0170/20090170305.pdf [firstpage_image] =>[orig_patent_app_number] => 12047485 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/047485
METHOD FOR IMPROVING ELECTROMIGRATION LIFETIME FOR CU INTERCONNECT SYSTEMS Mar 12, 2008 Abandoned
Array ( [id] => 4673352 [patent_doc_number] => 20080210980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-04 [patent_title] => 'Isolated CMOS transistors' [patent_app_type] => utility [patent_app_number] => 12/069941 [patent_app_country] => US [patent_app_date] => 2008-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 16741 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20080210980.pdf [firstpage_image] =>[orig_patent_app_number] => 12069941 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/069941
Isolated CMOS transistors Feb 13, 2008 Issued
Array ( [id] => 5391759 [patent_doc_number] => 20090209072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-20 [patent_title] => 'Methods Of Forming Transistor Gates, Methods Of Forming Memory Cells, And Methods Of Forming DRAM Arrays' [patent_app_type] => utility [patent_app_number] => 12/031015 [patent_app_country] => US [patent_app_date] => 2008-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3696 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0209/20090209072.pdf [firstpage_image] =>[orig_patent_app_number] => 12031015 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/031015
Methods of forming DRAM arrays Feb 13, 2008 Issued
Array ( [id] => 5480235 [patent_doc_number] => 20090203192 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-13 [patent_title] => 'Crack Stop Trenches' [patent_app_type] => utility [patent_app_number] => 12/030435 [patent_app_country] => US [patent_app_date] => 2008-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4517 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0203/20090203192.pdf [firstpage_image] =>[orig_patent_app_number] => 12030435 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/030435
Crack stop trenches Feb 12, 2008 Issued
Array ( [id] => 62884 [patent_doc_number] => 07763553 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-27 [patent_title] => 'Manufacturing method of semiconductor device subjected to heat treatment by use of optical heating apparatus' [patent_app_type] => utility [patent_app_number] => 12/025916 [patent_app_country] => US [patent_app_date] => 2008-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 41 [patent_no_of_words] => 12157 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/763/07763553.pdf [firstpage_image] =>[orig_patent_app_number] => 12025916 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/025916
Manufacturing method of semiconductor device subjected to heat treatment by use of optical heating apparatus Feb 4, 2008 Issued
Array ( [id] => 195801 [patent_doc_number] => 07635602 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-22 [patent_title] => 'Simulator of ion implantation and method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/013605 [patent_app_country] => US [patent_app_date] => 2008-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 43 [patent_no_of_words] => 8754 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/635/07635602.pdf [firstpage_image] =>[orig_patent_app_number] => 12013605 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/013605
Simulator of ion implantation and method for manufacturing semiconductor device Jan 13, 2008 Issued
Array ( [id] => 5342882 [patent_doc_number] => 20090181532 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-16 [patent_title] => 'INTEGRATION SCHEME FOR EXTENSION OF VIA OPENING DEPTH' [patent_app_type] => utility [patent_app_number] => 11/971996 [patent_app_country] => US [patent_app_date] => 2008-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6658 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20090181532.pdf [firstpage_image] =>[orig_patent_app_number] => 11971996 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/971996
INTEGRATION SCHEME FOR EXTENSION OF VIA OPENING DEPTH Jan 9, 2008 Abandoned
Array ( [id] => 4927530 [patent_doc_number] => 20080166893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-10 [patent_title] => 'LOW TEMPERATURE OXIDE FORMATION' [patent_app_type] => utility [patent_app_number] => 11/969125 [patent_app_country] => US [patent_app_date] => 2008-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2260 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20080166893.pdf [firstpage_image] =>[orig_patent_app_number] => 11969125 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/969125
LOW TEMPERATURE OXIDE FORMATION Jan 2, 2008 Abandoned
Array ( [id] => 5435687 [patent_doc_number] => 20090170274 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'METHOD OF FORMING METAL TRENCH PATTERN IN THIN-FILM DEVICE' [patent_app_type] => utility [patent_app_number] => 11/967905 [patent_app_country] => US [patent_app_date] => 2007-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 11855 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0170/20090170274.pdf [firstpage_image] =>[orig_patent_app_number] => 11967905 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/967905
Method of forming metal trench pattern in thin-film device Dec 30, 2007 Issued
Array ( [id] => 5435173 [patent_doc_number] => 20090169760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'COPPER METALLIZATION UTILIZING REFLOW ON NOBLE METAL LINERS' [patent_app_type] => utility [patent_app_number] => 11/968136 [patent_app_country] => US [patent_app_date] => 2007-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2232 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0169/20090169760.pdf [firstpage_image] =>[orig_patent_app_number] => 11968136 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/968136
COPPER METALLIZATION UTILIZING REFLOW ON NOBLE METAL LINERS Dec 30, 2007 Abandoned
Array ( [id] => 4608732 [patent_doc_number] => 07993971 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-09 [patent_title] => 'Forming a 3-D semiconductor die structure with an intermetallic formation' [patent_app_type] => utility [patent_app_number] => 11/966126 [patent_app_country] => US [patent_app_date] => 2007-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3619 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/993/07993971.pdf [firstpage_image] =>[orig_patent_app_number] => 11966126 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/966126
Forming a 3-D semiconductor die structure with an intermetallic formation Dec 27, 2007 Issued
Array ( [id] => 4852645 [patent_doc_number] => 20080318388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-25 [patent_title] => 'METHOD FOR FABRICATING MOS TRANSISTOR WITH RECESS CHANNEL' [patent_app_type] => utility [patent_app_number] => 11/955405 [patent_app_country] => US [patent_app_date] => 2007-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 2071 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0318/20080318388.pdf [firstpage_image] =>[orig_patent_app_number] => 11955405 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/955405
METHOD FOR FABRICATING MOS TRANSISTOR WITH RECESS CHANNEL Dec 12, 2007 Abandoned
Array ( [id] => 4873303 [patent_doc_number] => 20080200037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-21 [patent_title] => 'Method of thinning a wafer' [patent_app_type] => utility [patent_app_number] => 11/953846 [patent_app_country] => US [patent_app_date] => 2007-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 1768 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0200/20080200037.pdf [firstpage_image] =>[orig_patent_app_number] => 11953846 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/953846
Method of thinning a wafer Dec 9, 2007 Abandoned
Array ( [id] => 5419828 [patent_doc_number] => 20090146282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-11 [patent_title] => 'Semiconductor Package and Method of Forming Similar Structure for Top and Bottom Bonding Pads' [patent_app_type] => utility [patent_app_number] => 11/952502 [patent_app_country] => US [patent_app_date] => 2007-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4441 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20090146282.pdf [firstpage_image] =>[orig_patent_app_number] => 11952502 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/952502
Semiconductor package and method of forming similar structure for top and bottom bonding pads Dec 6, 2007 Issued
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