Search

Deven M. Collins

Examiner (ID: 5878)

Most Active Art Unit
2823
Art Unit(s)
2812, 2823, 2822
Total Applications
382
Issued Applications
374
Pending Applications
5
Abandoned Applications
3

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6224643 [patent_doc_number] => 20020004272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-10 [patent_title] => 'Multiple step methods for forming comformal layers' [patent_app_type] => new [patent_app_number] => 09/919313 [patent_app_country] => US [patent_app_date] => 2001-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7306 [patent_no_of_claims] => 86 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20020004272.pdf [firstpage_image] =>[orig_patent_app_number] => 09919313 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/919313
Multiple step methods for forming conformal layers Jul 30, 2001 Issued
Array ( [id] => 5888717 [patent_doc_number] => 20020013045 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-31 [patent_title] => 'Method for forming copper-containing metal studs' [patent_app_type] => new [patent_app_number] => 09/899873 [patent_app_country] => US [patent_app_date] => 2001-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4718 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20020013045.pdf [firstpage_image] =>[orig_patent_app_number] => 09899873 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/899873
Method for forming copper-containing metal studs Jul 4, 2001 Abandoned
Array ( [id] => 6961278 [patent_doc_number] => 20010012644 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-09 [patent_title] => 'Method for mounting a semiconductor chip on a substrate, and semiconductor device adapted for mounting on a substrate' [patent_app_type] => new [patent_app_number] => 09/828204 [patent_app_country] => US [patent_app_date] => 2001-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3834 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20010012644.pdf [firstpage_image] =>[orig_patent_app_number] => 09828204 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/828204
Method for mounting a semiconductor chip on a substrate, and semiconductor device adapted for mounting on a substrate Apr 8, 2001 Abandoned
Array ( [id] => 7645216 [patent_doc_number] => 06472756 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-10-29 [patent_title] => 'Method of forming titanium silicide and titanium by chemical vapor deposition and resulting apparatus' [patent_app_type] => B2 [patent_app_number] => 09/789999 [patent_app_country] => US [patent_app_date] => 2001-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3359 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/472/06472756.pdf [firstpage_image] =>[orig_patent_app_number] => 09789999 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/789999
Method of forming titanium silicide and titanium by chemical vapor deposition and resulting apparatus Feb 20, 2001 Issued
Array ( [id] => 6961325 [patent_doc_number] => 20010012665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-09 [patent_title] => 'Semiconductor device and method for fabricating the same' [patent_app_type] => new [patent_app_number] => 09/735909 [patent_app_country] => US [patent_app_date] => 2000-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4744 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20010012665.pdf [firstpage_image] =>[orig_patent_app_number] => 09735909 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/735909
Semiconductor device and method for fabricating the same Dec 13, 2000 Issued
Array ( [id] => 6883738 [patent_doc_number] => 20010037892 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-08 [patent_title] => 'Semiconductor package' [patent_app_type] => new [patent_app_number] => 09/731803 [patent_app_country] => US [patent_app_date] => 2000-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2339 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20010037892.pdf [firstpage_image] =>[orig_patent_app_number] => 09731803 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/731803
Semiconductor package Dec 7, 2000 Issued
Array ( [id] => 6875753 [patent_doc_number] => 20010000080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-03-29 [patent_title] => 'Semiconductor device and method of manufacturing the same, circuit board and electronic instrument' [patent_app_type] => new-utility [patent_app_number] => 09/729959 [patent_app_country] => US [patent_app_date] => 2000-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4486 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0000/20010000080.pdf [firstpage_image] =>[orig_patent_app_number] => 09729959 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/729959
Semiconductor device and method of manufacturing the same, circuit board and electronic instrument Dec 5, 2000 Issued
Array ( [id] => 1490050 [patent_doc_number] => 06417018 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'Asymmetrical molding method for multiple part matrixes' [patent_app_type] => B1 [patent_app_number] => 09/724470 [patent_app_country] => US [patent_app_date] => 2000-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 8906 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/417/06417018.pdf [firstpage_image] =>[orig_patent_app_number] => 09724470 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/724470
Asymmetrical molding method for multiple part matrixes Nov 27, 2000 Issued
Array ( [id] => 4303743 [patent_doc_number] => 06326265 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Device with embedded flash and EEPROM memories' [patent_app_type] => 1 [patent_app_number] => 9/713883 [patent_app_country] => US [patent_app_date] => 2000-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7364 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/326/06326265.pdf [firstpage_image] =>[orig_patent_app_number] => 713883 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/713883
Device with embedded flash and EEPROM memories Nov 15, 2000 Issued
Array ( [id] => 1587934 [patent_doc_number] => 06359335 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Method of manufacturing a plurality of semiconductor packages and the resulting semiconductor package structures' [patent_app_type] => B1 [patent_app_number] => 09/711036 [patent_app_country] => US [patent_app_date] => 2000-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 45 [patent_no_of_words] => 8465 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/359/06359335.pdf [firstpage_image] =>[orig_patent_app_number] => 09711036 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/711036
Method of manufacturing a plurality of semiconductor packages and the resulting semiconductor package structures Nov 12, 2000 Issued
Array ( [id] => 1561025 [patent_doc_number] => 06362022 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Multi-part lead frame with dissimilar materials and method of manufacturing' [patent_app_type] => B1 [patent_app_number] => 09/699538 [patent_app_country] => US [patent_app_date] => 2000-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 6380 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/362/06362022.pdf [firstpage_image] =>[orig_patent_app_number] => 09699538 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/699538
Multi-part lead frame with dissimilar materials and method of manufacturing Oct 29, 2000 Issued
Array ( [id] => 1507302 [patent_doc_number] => 06440791 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Self aligned bit-line contact opening and node contact opening fabrication process' [patent_app_type] => B1 [patent_app_number] => 09/690193 [patent_app_country] => US [patent_app_date] => 2000-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3030 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/440/06440791.pdf [firstpage_image] =>[orig_patent_app_number] => 09690193 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/690193
Self aligned bit-line contact opening and node contact opening fabrication process Oct 15, 2000 Issued
Array ( [id] => 1602549 [patent_doc_number] => 06432728 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Method for integration optimization by chemical mechanical planarization end-pointing technique' [patent_app_type] => B1 [patent_app_number] => 09/687163 [patent_app_country] => US [patent_app_date] => 2000-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 5509 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/432/06432728.pdf [firstpage_image] =>[orig_patent_app_number] => 09687163 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/687163
Method for integration optimization by chemical mechanical planarization end-pointing technique Oct 15, 2000 Issued
Array ( [id] => 1534478 [patent_doc_number] => 06489180 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-03 [patent_title] => 'Flip-chip packaging process utilizing no-flow underfill technique' [patent_app_type] => B1 [patent_app_number] => 09/685433 [patent_app_country] => US [patent_app_date] => 2000-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 2476 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/489/06489180.pdf [firstpage_image] =>[orig_patent_app_number] => 09685433 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/685433
Flip-chip packaging process utilizing no-flow underfill technique Oct 9, 2000 Issued
Array ( [id] => 1585349 [patent_doc_number] => 06358774 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/623883 [patent_app_country] => US [patent_app_date] => 2000-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3630 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/358/06358774.pdf [firstpage_image] =>[orig_patent_app_number] => 09623883 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/623883
Method of manufacturing a semiconductor device Sep 10, 2000 Issued
Array ( [id] => 1554697 [patent_doc_number] => 06348733 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-19 [patent_title] => 'Dual damascene process and structure with dielectric barrier layer' [patent_app_type] => B1 [patent_app_number] => 09/655087 [patent_app_country] => US [patent_app_date] => 2000-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 2282 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/348/06348733.pdf [firstpage_image] =>[orig_patent_app_number] => 09655087 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/655087
Dual damascene process and structure with dielectric barrier layer Sep 4, 2000 Issued
Array ( [id] => 1553576 [patent_doc_number] => 06348403 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-19 [patent_title] => 'Suppression of hillock formation in thin aluminum films' [patent_app_type] => B1 [patent_app_number] => 09/652423 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3543 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/348/06348403.pdf [firstpage_image] =>[orig_patent_app_number] => 09652423 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/652423
Suppression of hillock formation in thin aluminum films Aug 30, 2000 Issued
Array ( [id] => 1549668 [patent_doc_number] => 06346444 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-12 [patent_title] => 'Power semiconductor device using semi-insulating polycrystalline silicon and fabrication method thereof' [patent_app_type] => B1 [patent_app_number] => 09/653550 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 5926 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/346/06346444.pdf [firstpage_image] =>[orig_patent_app_number] => 09653550 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/653550
Power semiconductor device using semi-insulating polycrystalline silicon and fabrication method thereof Aug 30, 2000 Issued
Array ( [id] => 1462427 [patent_doc_number] => 06350633 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'Semiconductor chip assembly with simultaneously electroplated contact terminal and connection joint' [patent_app_type] => B1 [patent_app_number] => 09/643212 [patent_app_country] => US [patent_app_date] => 2000-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 7310 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/350/06350633.pdf [firstpage_image] =>[orig_patent_app_number] => 09643212 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/643212
Semiconductor chip assembly with simultaneously electroplated contact terminal and connection joint Aug 21, 2000 Issued
Array ( [id] => 1585582 [patent_doc_number] => 06358832 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Method of forming barrier layers for damascene interconnects' [patent_app_type] => B1 [patent_app_number] => 09/641834 [patent_app_country] => US [patent_app_date] => 2000-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 6114 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/358/06358832.pdf [firstpage_image] =>[orig_patent_app_number] => 09641834 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/641834
Method of forming barrier layers for damascene interconnects Aug 17, 2000 Issued
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