
Deven M. Collins
Examiner (ID: 5878)
| Most Active Art Unit | 2823 |
| Art Unit(s) | 2812, 2823, 2822 |
| Total Applications | 382 |
| Issued Applications | 374 |
| Pending Applications | 5 |
| Abandoned Applications | 3 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6224643
[patent_doc_number] => 20020004272
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-01-10
[patent_title] => 'Multiple step methods for forming comformal layers'
[patent_app_type] => new
[patent_app_number] => 09/919313
[patent_app_country] => US
[patent_app_date] => 2001-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 7306
[patent_no_of_claims] => 86
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[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0004/20020004272.pdf
[firstpage_image] =>[orig_patent_app_number] => 09919313
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/919313 | Multiple step methods for forming conformal layers | Jul 30, 2001 | Issued |
Array
(
[id] => 5888717
[patent_doc_number] => 20020013045
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-01-31
[patent_title] => 'Method for forming copper-containing metal studs'
[patent_app_type] => new
[patent_app_number] => 09/899873
[patent_app_country] => US
[patent_app_date] => 2001-07-05
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0013/20020013045.pdf
[firstpage_image] =>[orig_patent_app_number] => 09899873
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/899873 | Method for forming copper-containing metal studs | Jul 4, 2001 | Abandoned |
Array
(
[id] => 6961278
[patent_doc_number] => 20010012644
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[patent_kind] => A1
[patent_issue_date] => 2001-08-09
[patent_title] => 'Method for mounting a semiconductor chip on a substrate, and semiconductor device adapted for mounting on a substrate'
[patent_app_type] => new
[patent_app_number] => 09/828204
[patent_app_country] => US
[patent_app_date] => 2001-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/828204 | Method for mounting a semiconductor chip on a substrate, and semiconductor device adapted for mounting on a substrate | Apr 8, 2001 | Abandoned |
Array
(
[id] => 7645216
[patent_doc_number] => 06472756
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-10-29
[patent_title] => 'Method of forming titanium silicide and titanium by chemical vapor deposition and resulting apparatus'
[patent_app_type] => B2
[patent_app_number] => 09/789999
[patent_app_country] => US
[patent_app_date] => 2001-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 3359
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[firstpage_image] =>[orig_patent_app_number] => 09789999
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/789999 | Method of forming titanium silicide and titanium by chemical vapor deposition and resulting apparatus | Feb 20, 2001 | Issued |
Array
(
[id] => 6961325
[patent_doc_number] => 20010012665
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-08-09
[patent_title] => 'Semiconductor device and method for fabricating the same'
[patent_app_type] => new
[patent_app_number] => 09/735909
[patent_app_country] => US
[patent_app_date] => 2000-12-14
[patent_effective_date] => 0000-00-00
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Array
(
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[patent_doc_number] => 20010037892
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[patent_issue_date] => 2001-11-08
[patent_title] => 'Semiconductor package'
[patent_app_type] => new
[patent_app_number] => 09/731803
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 09731803
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/731803 | Semiconductor package | Dec 7, 2000 | Issued |
Array
(
[id] => 6875753
[patent_doc_number] => 20010000080
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[patent_title] => 'Semiconductor device and method of manufacturing the same, circuit board and electronic instrument'
[patent_app_type] => new-utility
[patent_app_number] => 09/729959
[patent_app_country] => US
[patent_app_date] => 2000-12-06
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Array
(
[id] => 1490050
[patent_doc_number] => 06417018
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-09
[patent_title] => 'Asymmetrical molding method for multiple part matrixes'
[patent_app_type] => B1
[patent_app_number] => 09/724470
[patent_app_country] => US
[patent_app_date] => 2000-11-28
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 09724470
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/724470 | Asymmetrical molding method for multiple part matrixes | Nov 27, 2000 | Issued |
Array
(
[id] => 4303743
[patent_doc_number] => 06326265
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-12-04
[patent_title] => 'Device with embedded flash and EEPROM memories'
[patent_app_type] => 1
[patent_app_number] => 9/713883
[patent_app_country] => US
[patent_app_date] => 2000-11-16
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[firstpage_image] =>[orig_patent_app_number] => 713883
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/713883 | Device with embedded flash and EEPROM memories | Nov 15, 2000 | Issued |
Array
(
[id] => 1587934
[patent_doc_number] => 06359335
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-03-19
[patent_title] => 'Method of manufacturing a plurality of semiconductor packages and the resulting semiconductor package structures'
[patent_app_type] => B1
[patent_app_number] => 09/711036
[patent_app_country] => US
[patent_app_date] => 2000-11-13
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/711036 | Method of manufacturing a plurality of semiconductor packages and the resulting semiconductor package structures | Nov 12, 2000 | Issued |
Array
(
[id] => 1561025
[patent_doc_number] => 06362022
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[patent_title] => 'Multi-part lead frame with dissimilar materials and method of manufacturing'
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Array
(
[id] => 1507302
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[patent_issue_date] => 2002-08-27
[patent_title] => 'Self aligned bit-line contact opening and node contact opening fabrication process'
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Array
(
[id] => 1602549
[patent_doc_number] => 06432728
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[patent_issue_date] => 2002-08-13
[patent_title] => 'Method for integration optimization by chemical mechanical planarization end-pointing technique'
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Array
(
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[patent_title] => 'Flip-chip packaging process utilizing no-flow underfill technique'
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Array
(
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Array
(
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[patent_title] => 'Dual damascene process and structure with dielectric barrier layer'
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Array
(
[id] => 1553576
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Array
(
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Array
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/641834 | Method of forming barrier layers for damascene interconnects | Aug 17, 2000 | Issued |