
Deven M. Collins
Examiner (ID: 7081)
| Most Active Art Unit | 2823 |
| Art Unit(s) | 2822, 2823, 2812 |
| Total Applications | 382 |
| Issued Applications | 374 |
| Pending Applications | 5 |
| Abandoned Applications | 3 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4191446
[patent_doc_number] => 06130141
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-10
[patent_title] => 'Flip chip metallization'
[patent_app_type] => 1
[patent_app_number] => 9/172467
[patent_app_country] => US
[patent_app_date] => 1998-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 3126
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/130/06130141.pdf
[firstpage_image] =>[orig_patent_app_number] => 172467
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/172467 | Flip chip metallization | Oct 13, 1998 | Issued |
Array
(
[id] => 4084057
[patent_doc_number] => 06162697
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-19
[patent_title] => 'High Q inductor realization for use in MMIC circuits'
[patent_app_type] => 1
[patent_app_number] => 9/170733
[patent_app_country] => US
[patent_app_date] => 1998-10-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 2879
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/162/06162697.pdf
[firstpage_image] =>[orig_patent_app_number] => 170733
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/170733 | High Q inductor realization for use in MMIC circuits | Oct 12, 1998 | Issued |
Array
(
[id] => 4145281
[patent_doc_number] => 06063646
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-16
[patent_title] => 'Method for production of semiconductor package'
[patent_app_type] => 1
[patent_app_number] => 9/167207
[patent_app_country] => US
[patent_app_date] => 1998-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 3315
[patent_no_of_claims] => 4
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[patent_words_short_claim] => 139
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[pdf_file] => patents/06/063/06063646.pdf
[firstpage_image] =>[orig_patent_app_number] => 167207
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/167207 | Method for production of semiconductor package | Oct 5, 1998 | Issued |
Array
(
[id] => 4107178
[patent_doc_number] => 06057178
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-02
[patent_title] => 'Method of padding an electronic component, mounted on a flat substrate, with a liquid filler'
[patent_app_type] => 1
[patent_app_number] => 9/160889
[patent_app_country] => US
[patent_app_date] => 1998-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 3
[patent_no_of_words] => 1639
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 122
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/057/06057178.pdf
[firstpage_image] =>[orig_patent_app_number] => 160889
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/160889 | Method of padding an electronic component, mounted on a flat substrate, with a liquid filler | Sep 24, 1998 | Issued |
Array
(
[id] => 4416904
[patent_doc_number] => 06194247
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-27
[patent_title] => 'Warp-resistent ultra-thin integrated circuit package fabrication method'
[patent_app_type] => 1
[patent_app_number] => 9/159120
[patent_app_country] => US
[patent_app_date] => 1998-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 5280
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[pdf_file] => patents/06/194/06194247.pdf
[firstpage_image] =>[orig_patent_app_number] => 159120
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/159120 | Warp-resistent ultra-thin integrated circuit package fabrication method | Sep 22, 1998 | Issued |
Array
(
[id] => 4116440
[patent_doc_number] => 06071761
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-06
[patent_title] => 'Method for encapsulated integrated circuits'
[patent_app_type] => 1
[patent_app_number] => 9/159537
[patent_app_country] => US
[patent_app_date] => 1998-09-23
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/071/06071761.pdf
[firstpage_image] =>[orig_patent_app_number] => 159537
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/159537 | Method for encapsulated integrated circuits | Sep 22, 1998 | Issued |
Array
(
[id] => 4191338
[patent_doc_number] => 06043144
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-28
[patent_title] => 'Bonding-pad structure for integrated circuit and method of fabricating the same'
[patent_app_type] => 1
[patent_app_number] => 9/152920
[patent_app_country] => US
[patent_app_date] => 1998-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 2869
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/043/06043144.pdf
[firstpage_image] =>[orig_patent_app_number] => 152920
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/152920 | Bonding-pad structure for integrated circuit and method of fabricating the same | Sep 13, 1998 | Issued |
Array
(
[id] => 4182646
[patent_doc_number] => 06159774
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-12
[patent_title] => 'Multi-layer interconnection layout between a chip core and peripheral devices'
[patent_app_type] => 1
[patent_app_number] => 9/151434
[patent_app_country] => US
[patent_app_date] => 1998-09-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 2378
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[patent_no_of_ind_claims] => 2
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/159/06159774.pdf
[firstpage_image] =>[orig_patent_app_number] => 151434
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/151434 | Multi-layer interconnection layout between a chip core and peripheral devices | Sep 10, 1998 | Issued |
Array
(
[id] => 4324904
[patent_doc_number] => 06249039
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-06-19
[patent_title] => 'Integrated inductive components and method of fabricating such components'
[patent_app_type] => 1
[patent_app_number] => 9/151410
[patent_app_country] => US
[patent_app_date] => 1998-09-10
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/249/06249039.pdf
[firstpage_image] =>[orig_patent_app_number] => 151410
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/151410 | Integrated inductive components and method of fabricating such components | Sep 9, 1998 | Issued |
Array
(
[id] => 4145837
[patent_doc_number] => 06063684
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-16
[patent_title] => 'Method for eliminating residual oxygen contaminations from crucible-drawn silicon wafers'
[patent_app_type] => 1
[patent_app_number] => 9/146967
[patent_app_country] => US
[patent_app_date] => 1998-09-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
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[patent_no_of_words] => 1906
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/063/06063684.pdf
[firstpage_image] =>[orig_patent_app_number] => 146967
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/146967 | Method for eliminating residual oxygen contaminations from crucible-drawn silicon wafers | Sep 3, 1998 | Issued |
Array
(
[id] => 4154841
[patent_doc_number] => 06114185
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-05
[patent_title] => 'Welding process and photovoltaic device'
[patent_app_type] => 1
[patent_app_number] => 9/140680
[patent_app_country] => US
[patent_app_date] => 1998-08-26
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/114/06114185.pdf
[firstpage_image] =>[orig_patent_app_number] => 140680
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/140680 | Welding process and photovoltaic device | Aug 25, 1998 | Issued |
Array
(
[id] => 4394376
[patent_doc_number] => 06297077
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-10-02
[patent_title] => 'Process for manufacturing chip cards, device for the implementation of this process and chip card'
[patent_app_type] => 1
[patent_app_number] => 9/135403
[patent_app_country] => US
[patent_app_date] => 1998-08-18
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 135403
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/135403 | Process for manufacturing chip cards, device for the implementation of this process and chip card | Aug 17, 1998 | Issued |
Array
(
[id] => 4236672
[patent_doc_number] => 06090643
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-18
[patent_title] => 'Semiconductor chip-substrate attachment structure'
[patent_app_type] => 1
[patent_app_number] => 9/135305
[patent_app_country] => US
[patent_app_date] => 1998-08-17
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[firstpage_image] =>[orig_patent_app_number] => 135305
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/135305 | Semiconductor chip-substrate attachment structure | Aug 16, 1998 | Issued |
Array
(
[id] => 4107152
[patent_doc_number] => 06057176
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-02
[patent_title] => 'Lead frame coining for semiconductor devices'
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[patent_app_number] => 9/133990
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[patent_app_date] => 1998-08-14
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/057/06057176.pdf
[firstpage_image] =>[orig_patent_app_number] => 133990
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/133990 | Lead frame coining for semiconductor devices | Aug 13, 1998 | Issued |
Array
(
[id] => 4101233
[patent_doc_number] => 06100114
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-08
[patent_title] => 'Encapsulation of solder bumps and solder connections'
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[patent_app_number] => 9/132127
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[patent_app_date] => 1998-08-10
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[pdf_file] => patents/06/100/06100114.pdf
[firstpage_image] =>[orig_patent_app_number] => 132127
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/132127 | Encapsulation of solder bumps and solder connections | Aug 9, 1998 | Issued |
Array
(
[id] => 4154782
[patent_doc_number] => 06114181
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-05
[patent_title] => 'Pre burn-in thermal bump card attach simulation to enhance reliability'
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[patent_app_number] => 9/129347
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[pdf_file] => patents/06/114/06114181.pdf
[firstpage_image] =>[orig_patent_app_number] => 129347
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/129347 | Pre burn-in thermal bump card attach simulation to enhance reliability | Aug 4, 1998 | Issued |
Array
(
[id] => 4235858
[patent_doc_number] => 06165892
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-26
[patent_title] => 'Method of planarizing thin film layers deposited over a common circuit base'
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[pdf_file] => patents/06/165/06165892.pdf
[firstpage_image] =>[orig_patent_app_number] => 127580
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/127580 | Method of planarizing thin film layers deposited over a common circuit base | Jul 30, 1998 | Issued |
Array
(
[id] => 4291495
[patent_doc_number] => 06180425
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[patent_issue_date] => 2001-01-30
[patent_title] => 'Data transfer circuit'
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[firstpage_image] =>[orig_patent_app_number] => 121247
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/121247 | Data transfer circuit | Jul 22, 1998 | Issued |
Array
(
[id] => 4204359
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[patent_issue_date] => 2000-06-20
[patent_title] => 'Semiconductor device evaluation method, method of controlling the semiconductor device production processes and recording medium'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/120890 | Semiconductor device evaluation method, method of controlling the semiconductor device production processes and recording medium | Jul 22, 1998 | Issued |
Array
(
[id] => 4106327
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[patent_title] => 'Integrated electro-optical package and method of fabrication'
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[pdf_file] => patents/06/022/06022760.pdf
[firstpage_image] =>[orig_patent_app_number] => 118879
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/118879 | Integrated electro-optical package and method of fabrication | Jul 19, 1998 | Issued |