
Deven M. Collins
Examiner (ID: 7081)
| Most Active Art Unit | 2823 |
| Art Unit(s) | 2822, 2823, 2812 |
| Total Applications | 382 |
| Issued Applications | 374 |
| Pending Applications | 5 |
| Abandoned Applications | 3 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4138951
[patent_doc_number] => 06060340
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-09
[patent_title] => 'Packing method of semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 9/116487
[patent_app_country] => US
[patent_app_date] => 1998-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 14
[patent_no_of_words] => 1217
[patent_no_of_claims] => 4
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[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/060/06060340.pdf
[firstpage_image] =>[orig_patent_app_number] => 116487
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/116487 | Packing method of semiconductor device | Jul 15, 1998 | Issued |
Array
(
[id] => 4154950
[patent_doc_number] => 06114192
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-05
[patent_title] => 'Method of manufacturing a semiconductor device having a ball grid array package structure using a supporting frame'
[patent_app_type] => 1
[patent_app_number] => 9/114997
[patent_app_country] => US
[patent_app_date] => 1998-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 41
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[patent_no_of_words] => 9667
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[patent_words_short_claim] => 102
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[pdf_file] => patents/06/114/06114192.pdf
[firstpage_image] =>[orig_patent_app_number] => 114997
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/114997 | Method of manufacturing a semiconductor device having a ball grid array package structure using a supporting frame | Jul 13, 1998 | Issued |
Array
(
[id] => 4101219
[patent_doc_number] => 06100113
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-08
[patent_title] => 'Very thin multi-chip-package and method of mass producing the same'
[patent_app_type] => 1
[patent_app_number] => 9/114314
[patent_app_country] => US
[patent_app_date] => 1998-07-13
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[patent_drawing_sheets_cnt] => 7
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[pdf_file] => patents/06/100/06100113.pdf
[firstpage_image] =>[orig_patent_app_number] => 114314
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/114314 | Very thin multi-chip-package and method of mass producing the same | Jul 12, 1998 | Issued |
Array
(
[id] => 3944163
[patent_doc_number] => 05976975
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-02
[patent_title] => 'Refractory metal capped low resistivity metal conductor lines and vias'
[patent_app_type] => 1
[patent_app_number] => 9/113917
[patent_app_country] => US
[patent_app_date] => 1998-07-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 6666
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[firstpage_image] =>[orig_patent_app_number] => 113917
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/113917 | Refractory metal capped low resistivity metal conductor lines and vias | Jul 9, 1998 | Issued |
Array
(
[id] => 4138912
[patent_doc_number] => 06060337
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-09
[patent_title] => 'Photoreflective detector including a light emitting element and a light receiving element located at different distances from an object reflecting light from the emitting element'
[patent_app_type] => 1
[patent_app_number] => 9/112207
[patent_app_country] => US
[patent_app_date] => 1998-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 33
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[pdf_file] => patents/06/060/06060337.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/112207 | Photoreflective detector including a light emitting element and a light receiving element located at different distances from an object reflecting light from the emitting element | Jul 8, 1998 | Issued |
Array
(
[id] => 4286488
[patent_doc_number] => 06268238
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-31
[patent_title] => 'Three dimensional package and architecture for high performance computer'
[patent_app_type] => 1
[patent_app_number] => 9/111507
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[pdf_file] => patents/06/268/06268238.pdf
[firstpage_image] =>[orig_patent_app_number] => 111507
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/111507 | Three dimensional package and architecture for high performance computer | Jul 7, 1998 | Issued |
Array
(
[id] => 4155633
[patent_doc_number] => 06114239
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[patent_kind] => NA
[patent_issue_date] => 2000-09-05
[patent_title] => 'Electronic circuit bonding interconnect component and flip chip interconnect bond'
[patent_app_type] => 1
[patent_app_number] => 9/111921
[patent_app_country] => US
[patent_app_date] => 1998-07-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[pdf_file] => patents/06/114/06114239.pdf
[firstpage_image] =>[orig_patent_app_number] => 111921
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/111921 | Electronic circuit bonding interconnect component and flip chip interconnect bond | Jul 7, 1998 | Issued |
Array
(
[id] => 4265676
[patent_doc_number] => 06259123
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-10
[patent_title] => 'High voltage power MOS device'
[patent_app_type] => 1
[patent_app_number] => 9/111151
[patent_app_country] => US
[patent_app_date] => 1998-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[pdf_file] => patents/06/259/06259123.pdf
[firstpage_image] =>[orig_patent_app_number] => 111151
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/111151 | High voltage power MOS device | Jul 5, 1998 | Issued |
Array
(
[id] => 3896281
[patent_doc_number] => 05897341
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-04-27
[patent_title] => 'Diffusion bonded interconnect'
[patent_app_type] => 1
[patent_app_number] => 9/109655
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[patent_app_date] => 1998-07-02
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/109655 | Diffusion bonded interconnect | Jul 1, 1998 | Issued |
Array
(
[id] => 4172837
[patent_doc_number] => 06083819
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-04
[patent_title] => 'Method and assembly for providing improved underchip encapsulation'
[patent_app_type] => 1
[patent_app_number] => 9/105749
[patent_app_country] => US
[patent_app_date] => 1998-06-26
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[patent_drawing_sheets_cnt] => 2
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[pdf_file] => patents/06/083/06083819.pdf
[firstpage_image] =>[orig_patent_app_number] => 105749
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/105749 | Method and assembly for providing improved underchip encapsulation | Jun 25, 1998 | Issued |
Array
(
[id] => 4236543
[patent_doc_number] => 06090634
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-18
[patent_title] => 'Failure analysis apparatus of semiconductor integrated circuits and method thereof'
[patent_app_type] => 1
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[pdf_file] => patents/06/090/06090634.pdf
[firstpage_image] =>[orig_patent_app_number] => 104877
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/104877 | Failure analysis apparatus of semiconductor integrated circuits and method thereof | Jun 24, 1998 | Issued |
Array
(
[id] => 4030762
[patent_doc_number] => 05963793
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-05
[patent_title] => 'Microelectronic packaging using arched solder columns'
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[patent_app_number] => 9/096754
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[firstpage_image] =>[orig_patent_app_number] => 096754
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/096754 | Microelectronic packaging using arched solder columns | Jun 11, 1998 | Issued |
Array
(
[id] => 3993412
[patent_doc_number] => 05985699
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[patent_kind] => NA
[patent_issue_date] => 1999-11-16
[patent_title] => 'Method for designing semiconductor integrated circuit'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/093757 | Method for designing semiconductor integrated circuit | Jun 8, 1998 | Issued |
Array
(
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[patent_issue_date] => 2001-01-09
[patent_title] => 'Multi-layer tab tape having distinct signal, power and ground planes, semiconductor device assembly employing same, apparatus for and method of assembling same'
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[pdf_file] => patents/06/171/06171888.pdf
[firstpage_image] =>[orig_patent_app_number] => 093437
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Array
(
[id] => 4107206
[patent_doc_number] => 06057180
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[patent_title] => 'Method of severing electrically conductive links with ultraviolet laser output'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/092490 | Method of severing electrically conductive links with ultraviolet laser output | Jun 4, 1998 | Issued |
Array
(
[id] => 4419848
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[patent_issue_date] => 2001-05-01
[patent_title] => 'Flip-chip integrated circuit routing to I/O devices'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/089703 | Flip-chip integrated circuit routing to I/O devices | Jun 2, 1998 | Issued |
Array
(
[id] => 4215032
[patent_doc_number] => 06110823
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-29
[patent_title] => 'Method of modifying the thickness of a plating on a member by creating a temperature gradient on the member, applications for employing such a method, and structures resulting from such a method'
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Array
(
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/088044 | Laser synthesized ceramic sensors and method for making | May 31, 1998 | Issued |
Array
(
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[pdf_file] => patents/05/923/05923958.pdf
[firstpage_image] =>[orig_patent_app_number] => 085450
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/085450 | Method for semiconductor chip packaging | May 27, 1998 | Issued |