Search

Deven M. Collins

Examiner (ID: 7081)

Most Active Art Unit
2823
Art Unit(s)
2822, 2823, 2812
Total Applications
382
Issued Applications
374
Pending Applications
5
Abandoned Applications
3

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3966813 [patent_doc_number] => 05956575 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Microconnectors' [patent_app_type] => 1 [patent_app_number] => 9/082505 [patent_app_country] => US [patent_app_date] => 1998-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 27 [patent_no_of_words] => 7189 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/956/05956575.pdf [firstpage_image] =>[orig_patent_app_number] => 082505 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/082505
Microconnectors May 20, 1998 Issued
Array ( [id] => 4064226 [patent_doc_number] => 06008113 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Process for wafer bonding in a vacuum' [patent_app_type] => 1 [patent_app_number] => 9/081696 [patent_app_country] => US [patent_app_date] => 1998-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 25 [patent_no_of_words] => 4596 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/008/06008113.pdf [firstpage_image] =>[orig_patent_app_number] => 081696 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/081696
Process for wafer bonding in a vacuum May 18, 1998 Issued
Array ( [id] => 4152718 [patent_doc_number] => 06107118 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Chip-contacting method requiring no contact bumps, and electronic circuit produced in this way' [patent_app_type] => 1 [patent_app_number] => 9/011570 [patent_app_country] => US [patent_app_date] => 1998-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2791 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/107/06107118.pdf [firstpage_image] =>[orig_patent_app_number] => 011570 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/011570
Chip-contacting method requiring no contact bumps, and electronic circuit produced in this way May 17, 1998 Issued
Array ( [id] => 3936759 [patent_doc_number] => 05915168 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-22 [patent_title] => 'Lid wafer bond packaging and micromachining' [patent_app_type] => 1 [patent_app_number] => 9/073776 [patent_app_country] => US [patent_app_date] => 1998-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 2743 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/915/05915168.pdf [firstpage_image] =>[orig_patent_app_number] => 073776 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/073776
Lid wafer bond packaging and micromachining May 5, 1998 Issued
Array ( [id] => 4204497 [patent_doc_number] => 06077728 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Method of producing a ceramic package main body' [patent_app_type] => 1 [patent_app_number] => 9/071814 [patent_app_country] => US [patent_app_date] => 1998-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 6692 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/077/06077728.pdf [firstpage_image] =>[orig_patent_app_number] => 071814 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/071814
Method of producing a ceramic package main body May 3, 1998 Issued
Array ( [id] => 4107662 [patent_doc_number] => 06057212 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Method for making bonded metal back-plane substrates' [patent_app_type] => 1 [patent_app_number] => 9/072294 [patent_app_country] => US [patent_app_date] => 1998-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3162 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/057/06057212.pdf [firstpage_image] =>[orig_patent_app_number] => 072294 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/072294
Method for making bonded metal back-plane substrates May 3, 1998 Issued
Array ( [id] => 4405059 [patent_doc_number] => 06232152 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Method of manufacturing a plurality of semiconductor packages and the resulting semiconductor package structures' [patent_app_type] => 1 [patent_app_number] => 9/067310 [patent_app_country] => US [patent_app_date] => 1998-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 48 [patent_no_of_words] => 8310 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/232/06232152.pdf [firstpage_image] =>[orig_patent_app_number] => 067310 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/067310
Method of manufacturing a plurality of semiconductor packages and the resulting semiconductor package structures Apr 27, 1998 Issued
Array ( [id] => 4090793 [patent_doc_number] => 05966630 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-12 [patent_title] => 'Wire bonding method' [patent_app_type] => 1 [patent_app_number] => 9/065694 [patent_app_country] => US [patent_app_date] => 1998-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 10 [patent_no_of_words] => 2203 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/966/05966630.pdf [firstpage_image] =>[orig_patent_app_number] => 065694 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/065694
Wire bonding method Apr 23, 1998 Issued
Array ( [id] => 3975993 [patent_doc_number] => 05937279 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Semiconductor device, and manufacturing method of the same' [patent_app_type] => 1 [patent_app_number] => 9/063380 [patent_app_country] => US [patent_app_date] => 1998-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 30 [patent_no_of_words] => 7894 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/937/05937279.pdf [firstpage_image] =>[orig_patent_app_number] => 063380 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/063380
Semiconductor device, and manufacturing method of the same Apr 20, 1998 Issued
Array ( [id] => 3896587 [patent_doc_number] => 05897362 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Bonding silicon wafers' [patent_app_type] => 1 [patent_app_number] => 9/062606 [patent_app_country] => US [patent_app_date] => 1998-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 6 [patent_no_of_words] => 1773 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/897/05897362.pdf [firstpage_image] =>[orig_patent_app_number] => 062606 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/062606
Bonding silicon wafers Apr 16, 1998 Issued
Array ( [id] => 4071106 [patent_doc_number] => 06069072 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-30 [patent_title] => 'CVD tin barrier layer for reduced electromigration of aluminum plugs' [patent_app_type] => 1 [patent_app_number] => 9/060920 [patent_app_country] => US [patent_app_date] => 1998-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3531 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/069/06069072.pdf [firstpage_image] =>[orig_patent_app_number] => 060920 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/060920
CVD tin barrier layer for reduced electromigration of aluminum plugs Apr 14, 1998 Issued
Array ( [id] => 3993949 [patent_doc_number] => 05918107 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'Method and system for fabricating and testing assemblies containing wire bonded semiconductor dice' [patent_app_type] => 1 [patent_app_number] => 9/059245 [patent_app_country] => US [patent_app_date] => 1998-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3293 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/918/05918107.pdf [firstpage_image] =>[orig_patent_app_number] => 059245 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/059245
Method and system for fabricating and testing assemblies containing wire bonded semiconductor dice Apr 12, 1998 Issued
Array ( [id] => 4069478 [patent_doc_number] => 05933713 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Method of forming overmolded chip scale package and resulting product' [patent_app_type] => 1 [patent_app_number] => 9/056124 [patent_app_country] => US [patent_app_date] => 1998-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 19 [patent_no_of_words] => 5365 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/933/05933713.pdf [firstpage_image] =>[orig_patent_app_number] => 056124 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/056124
Method of forming overmolded chip scale package and resulting product Apr 5, 1998 Issued
Array ( [id] => 3910265 [patent_doc_number] => 06001661 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Integrated circuit interconnect method and apparatus' [patent_app_type] => 1 [patent_app_number] => 9/055206 [patent_app_country] => US [patent_app_date] => 1998-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3651 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/001/06001661.pdf [firstpage_image] =>[orig_patent_app_number] => 055206 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/055206
Integrated circuit interconnect method and apparatus Apr 5, 1998 Issued
Array ( [id] => 4069449 [patent_doc_number] => 05933711 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Fabrication method for chip size semiconductor package' [patent_app_type] => 1 [patent_app_number] => 9/050917 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 20 [patent_no_of_words] => 1388 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/933/05933711.pdf [firstpage_image] =>[orig_patent_app_number] => 050917 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/050917
Fabrication method for chip size semiconductor package Mar 30, 1998 Issued
09/050106 SEMICONDUCTOR CHIPS HAVING A MESA STRUCTURE PROVIDED BY SAWING Mar 29, 1998 Issued
09/047884 LEAD FRAME WITH ELECTROSTATIC DISCHARGE PROTECTION Mar 24, 1998 Issued
Array ( [id] => 4235764 [patent_doc_number] => 06143628 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Semiconductor substrate and method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/047326 [patent_app_country] => US [patent_app_date] => 1998-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 25 [patent_no_of_words] => 16046 [patent_no_of_claims] => 82 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/143/06143628.pdf [firstpage_image] =>[orig_patent_app_number] => 047326 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/047326
Semiconductor substrate and method of manufacturing the same Mar 24, 1998 Issued
Array ( [id] => 4259304 [patent_doc_number] => 06258698 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Process for producing semiconductor substrate' [patent_app_type] => 1 [patent_app_number] => 9/046600 [patent_app_country] => US [patent_app_date] => 1998-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 29 [patent_no_of_words] => 8829 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/258/06258698.pdf [firstpage_image] =>[orig_patent_app_number] => 046600 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/046600
Process for producing semiconductor substrate Mar 23, 1998 Issued
Array ( [id] => 4069463 [patent_doc_number] => 05933712 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Attachment method for stacked integrated circuit (IC) chips' [patent_app_type] => 1 [patent_app_number] => 9/045626 [patent_app_country] => US [patent_app_date] => 1998-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 4965 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/933/05933712.pdf [firstpage_image] =>[orig_patent_app_number] => 045626 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/045626
Attachment method for stacked integrated circuit (IC) chips Mar 18, 1998 Issued
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