
Deven M. Collins
Examiner (ID: 15667)
| Most Active Art Unit | 2823 |
| Art Unit(s) | 2823, 2812, 2822 |
| Total Applications | 382 |
| Issued Applications | 374 |
| Pending Applications | 5 |
| Abandoned Applications | 3 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4380665
[patent_doc_number] => 06277670
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-08-21
[patent_title] => 'Semiconductor chip package and fabrication method thereof'
[patent_app_type] => 1
[patent_app_number] => 9/416272
[patent_app_country] => US
[patent_app_date] => 1999-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 3544
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[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/277/06277670.pdf
[firstpage_image] =>[orig_patent_app_number] => 416272
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/416272 | Semiconductor chip package and fabrication method thereof | Oct 11, 1999 | Issued |
Array
(
[id] => 4350820
[patent_doc_number] => 06291332
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-18
[patent_title] => 'Electroless plated semiconductor vias and channels'
[patent_app_type] => 1
[patent_app_number] => 9/416383
[patent_app_country] => US
[patent_app_date] => 1999-10-12
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/291/06291332.pdf
[firstpage_image] =>[orig_patent_app_number] => 416383
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/416383 | Electroless plated semiconductor vias and channels | Oct 11, 1999 | Issued |
Array
(
[id] => 1565607
[patent_doc_number] => 06376280
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-23
[patent_title] => 'Microcap wafer-level package'
[patent_app_type] => B1
[patent_app_number] => 09/415284
[patent_app_country] => US
[patent_app_date] => 1999-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/415284 | Microcap wafer-level package | Oct 7, 1999 | Issued |
Array
(
[id] => 4363747
[patent_doc_number] => 06169324
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[patent_kind] => NA
[patent_issue_date] => 2001-01-02
[patent_title] => 'Semiconductor integrated circuit device, process for fabricating the same, and apparatus for fabricating the same'
[patent_app_type] => 1
[patent_app_number] => 9/413754
[patent_app_country] => US
[patent_app_date] => 1999-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 70
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[patent_no_of_words] => 55657
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[pdf_file] => patents/06/169/06169324.pdf
[firstpage_image] =>[orig_patent_app_number] => 413754
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/413754 | Semiconductor integrated circuit device, process for fabricating the same, and apparatus for fabricating the same | Oct 5, 1999 | Issued |
Array
(
[id] => 4350806
[patent_doc_number] => 06291331
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-18
[patent_title] => 'Re-deposition high compressive stress PECVD oxide film after IMD CMP process to solve more than 5 metal stack via process IMD crack issue'
[patent_app_type] => 1
[patent_app_number] => 9/412654
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[patent_app_date] => 1999-10-04
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[pdf_file] => patents/06/291/06291331.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/412654 | Re-deposition high compressive stress PECVD oxide film after IMD CMP process to solve more than 5 metal stack via process IMD crack issue | Oct 3, 1999 | Issued |
Array
(
[id] => 4195307
[patent_doc_number] => 06153935
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[patent_issue_date] => 2000-11-28
[patent_title] => 'Dual etch stop/diffusion barrier for damascene interconnects'
[patent_app_type] => 1
[patent_app_number] => 9/409244
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[patent_app_date] => 1999-09-30
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Array
(
[id] => 4286459
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[patent_issue_date] => 2001-07-31
[patent_title] => 'Method of manufacturing a semiconductor device having a package structure, and semiconductor device manufactured thereby'
[patent_app_type] => 1
[patent_app_number] => 9/408844
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[patent_app_date] => 1999-09-30
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/408844 | Method of manufacturing a semiconductor device having a package structure, and semiconductor device manufactured thereby | Sep 29, 1999 | Issued |
Array
(
[id] => 4162934
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[patent_issue_date] => 2000-12-05
[patent_title] => 'Reduced variation in interconnect resistance using run-to-run control of chemical-mechanical polishing during semiconductor fabrication'
[patent_app_type] => 1
[patent_app_number] => 9/401914
[patent_app_country] => US
[patent_app_date] => 1999-09-23
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/401914 | Reduced variation in interconnect resistance using run-to-run control of chemical-mechanical polishing during semiconductor fabrication | Sep 22, 1999 | Issued |
Array
(
[id] => 4422734
[patent_doc_number] => 06194780
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[patent_issue_date] => 2001-02-27
[patent_title] => 'Tape automated bonding method and bonded structure'
[patent_app_type] => 1
[patent_app_number] => 9/400633
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/400633 | Tape automated bonding method and bonded structure | Sep 22, 1999 | Issued |
Array
(
[id] => 4322014
[patent_doc_number] => 06331479
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[patent_issue_date] => 2001-12-18
[patent_title] => 'Method to prevent degradation of low dielectric constant material in copper damascene interconnects'
[patent_app_type] => 1
[patent_app_number] => 9/398294
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[patent_app_date] => 1999-09-20
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/398294 | Method to prevent degradation of low dielectric constant material in copper damascene interconnects | Sep 19, 1999 | Issued |
Array
(
[id] => 4274819
[patent_doc_number] => 06281040
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[patent_issue_date] => 2001-08-28
[patent_title] => 'Methods for making circuit substrates and electrical assemblies'
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[patent_app_country] => US
[patent_app_date] => 1999-09-16
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/397614 | Methods for making circuit substrates and electrical assemblies | Sep 15, 1999 | Issued |
Array
(
[id] => 4270683
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[patent_issue_date] => 2001-11-27
[patent_title] => 'Wafer coating method for flip chips'
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Array
(
[id] => 4368408
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[patent_issue_date] => 2001-09-11
[patent_title] => 'Method for manufacturing lead frames and lead frame material for semiconductor device'
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Array
(
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[patent_title] => 'Interconnect structure for joining a chip to a circuit card'
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Array
(
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[patent_title] => 'Substrate structure for improving attachment reliability of semiconductor chips and modules'
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Array
(
[id] => 4089830
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[patent_title] => 'Integrated circuit bonding pads including intermediate closed conductive layers having spaced apart insulating islands therein'
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Array
(
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Array
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Array
(
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/383733 | Navigation using 3-D detectable pattern | Aug 25, 1999 | Issued |