Search

Deven M. Collins

Examiner (ID: 15667)

Most Active Art Unit
2823
Art Unit(s)
2823, 2812, 2822
Total Applications
382
Issued Applications
374
Pending Applications
5
Abandoned Applications
3

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4380665 [patent_doc_number] => 06277670 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Semiconductor chip package and fabrication method thereof' [patent_app_type] => 1 [patent_app_number] => 9/416272 [patent_app_country] => US [patent_app_date] => 1999-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 3544 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/277/06277670.pdf [firstpage_image] =>[orig_patent_app_number] => 416272 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/416272
Semiconductor chip package and fabrication method thereof Oct 11, 1999 Issued
Array ( [id] => 4350820 [patent_doc_number] => 06291332 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Electroless plated semiconductor vias and channels' [patent_app_type] => 1 [patent_app_number] => 9/416383 [patent_app_country] => US [patent_app_date] => 1999-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4118 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/291/06291332.pdf [firstpage_image] =>[orig_patent_app_number] => 416383 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/416383
Electroless plated semiconductor vias and channels Oct 11, 1999 Issued
Array ( [id] => 1565607 [patent_doc_number] => 06376280 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Microcap wafer-level package' [patent_app_type] => B1 [patent_app_number] => 09/415284 [patent_app_country] => US [patent_app_date] => 1999-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 5894 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/376/06376280.pdf [firstpage_image] =>[orig_patent_app_number] => 09415284 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/415284
Microcap wafer-level package Oct 7, 1999 Issued
Array ( [id] => 4363747 [patent_doc_number] => 06169324 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Semiconductor integrated circuit device, process for fabricating the same, and apparatus for fabricating the same' [patent_app_type] => 1 [patent_app_number] => 9/413754 [patent_app_country] => US [patent_app_date] => 1999-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 70 [patent_figures_cnt] => 115 [patent_no_of_words] => 55657 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/169/06169324.pdf [firstpage_image] =>[orig_patent_app_number] => 413754 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/413754
Semiconductor integrated circuit device, process for fabricating the same, and apparatus for fabricating the same Oct 5, 1999 Issued
Array ( [id] => 4350806 [patent_doc_number] => 06291331 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Re-deposition high compressive stress PECVD oxide film after IMD CMP process to solve more than 5 metal stack via process IMD crack issue' [patent_app_type] => 1 [patent_app_number] => 9/412654 [patent_app_country] => US [patent_app_date] => 1999-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4479 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 337 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/291/06291331.pdf [firstpage_image] =>[orig_patent_app_number] => 412654 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/412654
Re-deposition high compressive stress PECVD oxide film after IMD CMP process to solve more than 5 metal stack via process IMD crack issue Oct 3, 1999 Issued
Array ( [id] => 4195307 [patent_doc_number] => 06153935 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Dual etch stop/diffusion barrier for damascene interconnects' [patent_app_type] => 1 [patent_app_number] => 9/409244 [patent_app_country] => US [patent_app_date] => 1999-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 6052 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/153/06153935.pdf [firstpage_image] =>[orig_patent_app_number] => 409244 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/409244
Dual etch stop/diffusion barrier for damascene interconnects Sep 29, 1999 Issued
Array ( [id] => 4286459 [patent_doc_number] => 06268236 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Method of manufacturing a semiconductor device having a package structure, and semiconductor device manufactured thereby' [patent_app_type] => 1 [patent_app_number] => 9/408844 [patent_app_country] => US [patent_app_date] => 1999-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4686 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/268/06268236.pdf [firstpage_image] =>[orig_patent_app_number] => 408844 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/408844
Method of manufacturing a semiconductor device having a package structure, and semiconductor device manufactured thereby Sep 29, 1999 Issued
Array ( [id] => 4162934 [patent_doc_number] => 06157078 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Reduced variation in interconnect resistance using run-to-run control of chemical-mechanical polishing during semiconductor fabrication' [patent_app_type] => 1 [patent_app_number] => 9/401914 [patent_app_country] => US [patent_app_date] => 1999-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5653 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/157/06157078.pdf [firstpage_image] =>[orig_patent_app_number] => 401914 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/401914
Reduced variation in interconnect resistance using run-to-run control of chemical-mechanical polishing during semiconductor fabrication Sep 22, 1999 Issued
Array ( [id] => 4422734 [patent_doc_number] => 06194780 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Tape automated bonding method and bonded structure' [patent_app_type] => 1 [patent_app_number] => 9/400633 [patent_app_country] => US [patent_app_date] => 1999-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 23 [patent_no_of_words] => 4028 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/194/06194780.pdf [firstpage_image] =>[orig_patent_app_number] => 400633 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/400633
Tape automated bonding method and bonded structure Sep 22, 1999 Issued
Array ( [id] => 4322014 [patent_doc_number] => 06331479 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-18 [patent_title] => 'Method to prevent degradation of low dielectric constant material in copper damascene interconnects' [patent_app_type] => 1 [patent_app_number] => 9/398294 [patent_app_country] => US [patent_app_date] => 1999-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 3345 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/331/06331479.pdf [firstpage_image] =>[orig_patent_app_number] => 398294 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/398294
Method to prevent degradation of low dielectric constant material in copper damascene interconnects Sep 19, 1999 Issued
Array ( [id] => 4274819 [patent_doc_number] => 06281040 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Methods for making circuit substrates and electrical assemblies' [patent_app_type] => 1 [patent_app_number] => 9/397614 [patent_app_country] => US [patent_app_date] => 1999-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 9126 [patent_no_of_claims] => 89 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/281/06281040.pdf [firstpage_image] =>[orig_patent_app_number] => 397614 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/397614
Methods for making circuit substrates and electrical assemblies Sep 15, 1999 Issued
Array ( [id] => 4270683 [patent_doc_number] => 06323062 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Wafer coating method for flip chips' [patent_app_type] => 1 [patent_app_number] => 9/395553 [patent_app_country] => US [patent_app_date] => 1999-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 3296 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/323/06323062.pdf [firstpage_image] =>[orig_patent_app_number] => 395553 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/395553
Wafer coating method for flip chips Sep 13, 1999 Issued
Array ( [id] => 4368408 [patent_doc_number] => 06287896 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Method for manufacturing lead frames and lead frame material for semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/396494 [patent_app_country] => US [patent_app_date] => 1999-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2950 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/287/06287896.pdf [firstpage_image] =>[orig_patent_app_number] => 396494 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/396494
Method for manufacturing lead frames and lead frame material for semiconductor device Sep 12, 1999 Issued
Array ( [id] => 4130810 [patent_doc_number] => 06121069 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Interconnect structure for joining a chip to a circuit card' [patent_app_type] => 1 [patent_app_number] => 9/390084 [patent_app_country] => US [patent_app_date] => 1999-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 5908 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/121/06121069.pdf [firstpage_image] =>[orig_patent_app_number] => 390084 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/390084
Interconnect structure for joining a chip to a circuit card Sep 2, 1999 Issued
Array ( [id] => 4282911 [patent_doc_number] => 06281581 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Substrate structure for improving attachment reliability of semiconductor chips and modules' [patent_app_type] => 1 [patent_app_number] => 9/388753 [patent_app_country] => US [patent_app_date] => 1999-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 20 [patent_no_of_words] => 4510 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/281/06281581.pdf [firstpage_image] =>[orig_patent_app_number] => 388753 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/388753
Substrate structure for improving attachment reliability of semiconductor chips and modules Sep 1, 1999 Issued
Array ( [id] => 4089830 [patent_doc_number] => 06163074 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Integrated circuit bonding pads including intermediate closed conductive layers having spaced apart insulating islands therein' [patent_app_type] => 1 [patent_app_number] => 9/387954 [patent_app_country] => US [patent_app_date] => 1999-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 22 [patent_no_of_words] => 5065 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/163/06163074.pdf [firstpage_image] =>[orig_patent_app_number] => 387954 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/387954
Integrated circuit bonding pads including intermediate closed conductive layers having spaced apart insulating islands therein Aug 31, 1999 Issued
Array ( [id] => 4176902 [patent_doc_number] => 06140701 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Suppression of hillock formation in thin aluminum films' [patent_app_type] => 1 [patent_app_number] => 9/387133 [patent_app_country] => US [patent_app_date] => 1999-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3582 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/140/06140701.pdf [firstpage_image] =>[orig_patent_app_number] => 387133 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/387133
Suppression of hillock formation in thin aluminum films Aug 30, 1999 Issued
Array ( [id] => 4387500 [patent_doc_number] => 06294825 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Asymmetrical mold of multiple-part matrixes' [patent_app_type] => 1 [patent_app_number] => 9/385981 [patent_app_country] => US [patent_app_date] => 1999-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 8904 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/294/06294825.pdf [firstpage_image] =>[orig_patent_app_number] => 385981 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/385981
Asymmetrical mold of multiple-part matrixes Aug 29, 1999 Issued
Array ( [id] => 4239511 [patent_doc_number] => 06118179 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Semiconductor component with external contact polymer support member and method of fabrication' [patent_app_type] => 1 [patent_app_number] => 9/384783 [patent_app_country] => US [patent_app_date] => 1999-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 22 [patent_no_of_words] => 5324 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/118/06118179.pdf [firstpage_image] =>[orig_patent_app_number] => 384783 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/384783
Semiconductor component with external contact polymer support member and method of fabrication Aug 26, 1999 Issued
Array ( [id] => 1553423 [patent_doc_number] => 06348364 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-19 [patent_title] => 'Navigation using 3-D detectable pattern' [patent_app_type] => B1 [patent_app_number] => 09/383733 [patent_app_country] => US [patent_app_date] => 1999-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 4268 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/348/06348364.pdf [firstpage_image] =>[orig_patent_app_number] => 09383733 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/383733
Navigation using 3-D detectable pattern Aug 25, 1999 Issued
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