
Deven M. Collins
Examiner (ID: 15667)
| Most Active Art Unit | 2823 |
| Art Unit(s) | 2823, 2812, 2822 |
| Total Applications | 382 |
| Issued Applications | 374 |
| Pending Applications | 5 |
| Abandoned Applications | 3 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4380890
[patent_doc_number] => 06294407
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-25
[patent_title] => 'Microelectronic packages including thin film decal and dielectric adhesive layer having conductive vias therein, and methods of fabricating the same'
[patent_app_type] => 1
[patent_app_number] => 9/306463
[patent_app_country] => US
[patent_app_date] => 1999-05-05
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/294/06294407.pdf
[firstpage_image] =>[orig_patent_app_number] => 306463
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/306463 | Microelectronic packages including thin film decal and dielectric adhesive layer having conductive vias therein, and methods of fabricating the same | May 4, 1999 | Issued |
Array
(
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[patent_doc_number] => 06204095
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[patent_kind] => NA
[patent_issue_date] => 2001-03-20
[patent_title] => 'Method of forming overmolded chip scale package and resulting product'
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[patent_app_date] => 1999-05-04
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Array
(
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[patent_issue_date] => 2001-05-01
[patent_title] => 'Method of producing a thin layer of semiconductor material'
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[patent_app_number] => 9/299683
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Array
(
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[patent_doc_number] => 06117762
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[patent_kind] => NA
[patent_issue_date] => 2000-09-12
[patent_title] => 'Method and apparatus using silicide layer for protecting integrated circuits from reverse engineering'
[patent_app_type] => 1
[patent_app_number] => 9/298293
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[patent_app_date] => 1999-04-23
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Array
(
[id] => 4419594
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[patent_issue_date] => 2001-01-23
[patent_title] => 'Integrated circuit structures having gas pockets and method for forming integrated circuit structures having gas pockets'
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Array
(
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[patent_doc_number] => 06140150
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[patent_title] => 'Plastic encapsulation for integrated circuits having plated copper top surface level interconnect'
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Array
(
[id] => 4408285
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[patent_title] => 'Apparatus and method for automating the underfill of flip-chip devices'
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[patent_app_number] => 9/289883
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/289883 | Apparatus and method for automating the underfill of flip-chip devices | Apr 8, 1999 | Issued |
Array
(
[id] => 4232441
[patent_doc_number] => 06117704
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[patent_issue_date] => 2000-09-12
[patent_title] => 'Stackable layers containing encapsulated chips'
[patent_app_type] => 1
[patent_app_number] => 9/282704
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/282704 | Stackable layers containing encapsulated chips | Mar 30, 1999 | Issued |
Array
(
[id] => 4290059
[patent_doc_number] => 06235616
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[patent_issue_date] => 2001-05-22
[patent_title] => 'Method of ion implantation into silicon carbide semiconductors'
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[patent_app_date] => 1999-03-29
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Array
(
[id] => 4094194
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[patent_issue_date] => 2000-08-01
[patent_title] => 'Method for controlling the thickness of a passivation layer on a semiconductor device'
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[patent_app_number] => 9/276260
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[patent_app_date] => 1999-03-25
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Array
(
[id] => 4318859
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[patent_title] => 'Fabrication of integrated circuits on both sides of a semiconductor wafer'
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Array
(
[id] => 4249305
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[patent_title] => 'Process for manufacturing semiconductor wafer, process for manufacturing semiconductor chip, and IC card'
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Array
(
[id] => 4101068
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Array
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Array
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Array
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Array
(
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/255554 | Asymmetric transfer molding method and an asymmetric encapsulation made therefrom | Feb 21, 1999 | Issued |