Search

Deven M. Collins

Examiner (ID: 15667)

Most Active Art Unit
2823
Art Unit(s)
2823, 2812, 2822
Total Applications
382
Issued Applications
374
Pending Applications
5
Abandoned Applications
3

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4380890 [patent_doc_number] => 06294407 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Microelectronic packages including thin film decal and dielectric adhesive layer having conductive vias therein, and methods of fabricating the same' [patent_app_type] => 1 [patent_app_number] => 9/306463 [patent_app_country] => US [patent_app_date] => 1999-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 9092 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/294/06294407.pdf [firstpage_image] =>[orig_patent_app_number] => 306463 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/306463
Microelectronic packages including thin film decal and dielectric adhesive layer having conductive vias therein, and methods of fabricating the same May 4, 1999 Issued
Array ( [id] => 4257850 [patent_doc_number] => 06204095 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Method of forming overmolded chip scale package and resulting product' [patent_app_type] => 1 [patent_app_number] => 9/304368 [patent_app_country] => US [patent_app_date] => 1999-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 19 [patent_no_of_words] => 5386 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/204/06204095.pdf [firstpage_image] =>[orig_patent_app_number] => 304368 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/304368
Method of forming overmolded chip scale package and resulting product May 3, 1999 Issued
Array ( [id] => 4420354 [patent_doc_number] => 06225192 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Method of producing a thin layer of semiconductor material' [patent_app_type] => 1 [patent_app_number] => 9/299683 [patent_app_country] => US [patent_app_date] => 1999-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3569 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/225/06225192.pdf [firstpage_image] =>[orig_patent_app_number] => 299683 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/299683
Method of producing a thin layer of semiconductor material Apr 25, 1999 Issued
Array ( [id] => 4233299 [patent_doc_number] => 06117762 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Method and apparatus using silicide layer for protecting integrated circuits from reverse engineering' [patent_app_type] => 1 [patent_app_number] => 9/298293 [patent_app_country] => US [patent_app_date] => 1999-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2800 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/117/06117762.pdf [firstpage_image] =>[orig_patent_app_number] => 298293 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/298293
Method and apparatus using silicide layer for protecting integrated circuits from reverse engineering Apr 22, 1999 Issued
Array ( [id] => 4419594 [patent_doc_number] => 06177329 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'Integrated circuit structures having gas pockets and method for forming integrated circuit structures having gas pockets' [patent_app_type] => 1 [patent_app_number] => 9/292174 [patent_app_country] => US [patent_app_date] => 1999-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 27 [patent_no_of_words] => 7332 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/177/06177329.pdf [firstpage_image] =>[orig_patent_app_number] => 292174 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/292174
Integrated circuit structures having gas pockets and method for forming integrated circuit structures having gas pockets Apr 14, 1999 Issued
Array ( [id] => 4168591 [patent_doc_number] => 06140150 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Plastic encapsulation for integrated circuits having plated copper top surface level interconnect' [patent_app_type] => 1 [patent_app_number] => 9/291884 [patent_app_country] => US [patent_app_date] => 1999-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 3366 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/140/06140150.pdf [firstpage_image] =>[orig_patent_app_number] => 291884 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/291884
Plastic encapsulation for integrated circuits having plated copper top surface level interconnect Apr 13, 1999 Issued
Array ( [id] => 4408285 [patent_doc_number] => 06228679 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Apparatus and method for automating the underfill of flip-chip devices' [patent_app_type] => 1 [patent_app_number] => 9/289883 [patent_app_country] => US [patent_app_date] => 1999-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2531 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/228/06228679.pdf [firstpage_image] =>[orig_patent_app_number] => 289883 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/289883
Apparatus and method for automating the underfill of flip-chip devices Apr 8, 1999 Issued
Array ( [id] => 4232441 [patent_doc_number] => 06117704 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Stackable layers containing encapsulated chips' [patent_app_type] => 1 [patent_app_number] => 9/282704 [patent_app_country] => US [patent_app_date] => 1999-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 26 [patent_no_of_words] => 3291 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/117/06117704.pdf [firstpage_image] =>[orig_patent_app_number] => 282704 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/282704
Stackable layers containing encapsulated chips Mar 30, 1999 Issued
Array ( [id] => 4290059 [patent_doc_number] => 06235616 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Method of ion implantation into silicon carbide semiconductors' [patent_app_type] => 1 [patent_app_number] => 9/277733 [patent_app_country] => US [patent_app_date] => 1999-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1131 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/235/06235616.pdf [firstpage_image] =>[orig_patent_app_number] => 277733 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/277733
Method of ion implantation into silicon carbide semiconductors Mar 28, 1999 Issued
Array ( [id] => 4094194 [patent_doc_number] => 06096579 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Method for controlling the thickness of a passivation layer on a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/276260 [patent_app_country] => US [patent_app_date] => 1999-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3190 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/096/06096579.pdf [firstpage_image] =>[orig_patent_app_number] => 276260 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/276260
Method for controlling the thickness of a passivation layer on a semiconductor device Mar 24, 1999 Issued
Array ( [id] => 4318859 [patent_doc_number] => 06248647 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Fabrication of integrated circuits on both sides of a semiconductor wafer' [patent_app_type] => 1 [patent_app_number] => 9/270257 [patent_app_country] => US [patent_app_date] => 1999-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 3581 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/248/06248647.pdf [firstpage_image] =>[orig_patent_app_number] => 270257 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/270257
Fabrication of integrated circuits on both sides of a semiconductor wafer Mar 14, 1999 Issued
Array ( [id] => 4249305 [patent_doc_number] => 06207473 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Process for manufacturing semiconductor wafer, process for manufacturing semiconductor chip, and IC card' [patent_app_type] => 1 [patent_app_number] => 9/147824 [patent_app_country] => US [patent_app_date] => 1999-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 4143 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/207/06207473.pdf [firstpage_image] =>[orig_patent_app_number] => 147824 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/147824
Process for manufacturing semiconductor wafer, process for manufacturing semiconductor chip, and IC card Mar 14, 1999 Issued
Array ( [id] => 4101068 [patent_doc_number] => 06100102 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Method of in-line monitoring for shallow pit on semiconductor substrate' [patent_app_type] => 1 [patent_app_number] => 9/265840 [patent_app_country] => US [patent_app_date] => 1999-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2466 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/100/06100102.pdf [firstpage_image] =>[orig_patent_app_number] => 265840 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/265840
Method of in-line monitoring for shallow pit on semiconductor substrate Mar 9, 1999 Issued
Array ( [id] => 4358485 [patent_doc_number] => 06255188 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Method of removing a polysilicon buffer using an etching selectivity solution' [patent_app_type] => 1 [patent_app_number] => 9/264600 [patent_app_country] => US [patent_app_date] => 1999-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3365 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/255/06255188.pdf [firstpage_image] =>[orig_patent_app_number] => 264600 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/264600
Method of removing a polysilicon buffer using an etching selectivity solution Mar 7, 1999 Issued
Array ( [id] => 4107055 [patent_doc_number] => 06057170 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Method of measuring waviness in silicon wafers' [patent_app_type] => 1 [patent_app_number] => 9/264230 [patent_app_country] => US [patent_app_date] => 1999-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2800 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/057/06057170.pdf [firstpage_image] =>[orig_patent_app_number] => 264230 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/264230
Method of measuring waviness in silicon wafers Mar 4, 1999 Issued
Array ( [id] => 4310066 [patent_doc_number] => 06326673 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Method and structure of manufacturing a high-Q inductor with an air trench' [patent_app_type] => 1 [patent_app_number] => 9/260597 [patent_app_country] => US [patent_app_date] => 1999-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 2583 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/326/06326673.pdf [firstpage_image] =>[orig_patent_app_number] => 260597 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/260597
Method and structure of manufacturing a high-Q inductor with an air trench Mar 1, 1999 Issued
Array ( [id] => 4365074 [patent_doc_number] => 06191493 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Resin seal semiconductor package and manufacturing method of the same' [patent_app_type] => 1 [patent_app_number] => 9/260594 [patent_app_country] => US [patent_app_date] => 1999-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 67 [patent_figures_cnt] => 115 [patent_no_of_words] => 22792 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/191/06191493.pdf [firstpage_image] =>[orig_patent_app_number] => 260594 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/260594
Resin seal semiconductor package and manufacturing method of the same Mar 1, 1999 Issued
Array ( [id] => 1564795 [patent_doc_number] => 06338971 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-15 [patent_title] => 'Method of correcting alignment' [patent_app_type] => B1 [patent_app_number] => 09/256217 [patent_app_country] => US [patent_app_date] => 1999-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 68 [patent_no_of_words] => 20271 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/338/06338971.pdf [firstpage_image] =>[orig_patent_app_number] => 09256217 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/256217
Method of correcting alignment Feb 23, 1999 Issued
Array ( [id] => 4286419 [patent_doc_number] => 06211049 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Forming submicron integrated-circuit wiring from gold, silver, copper, and other metals' [patent_app_type] => 1 [patent_app_number] => 9/256123 [patent_app_country] => US [patent_app_date] => 1999-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3788 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/211/06211049.pdf [firstpage_image] =>[orig_patent_app_number] => 256123 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/256123
Forming submicron integrated-circuit wiring from gold, silver, copper, and other metals Feb 23, 1999 Issued
Array ( [id] => 4235083 [patent_doc_number] => 06143581 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Asymmetric transfer molding method and an asymmetric encapsulation made therefrom' [patent_app_type] => 1 [patent_app_number] => 9/255554 [patent_app_country] => US [patent_app_date] => 1999-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 2622 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/143/06143581.pdf [firstpage_image] =>[orig_patent_app_number] => 255554 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/255554
Asymmetric transfer molding method and an asymmetric encapsulation made therefrom Feb 21, 1999 Issued
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