Devon C. Kramer

Array ( [id] => 6012311 [patent_doc_number] => 20020100934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-01 [patent_title] => 'High voltage semiconductor device' [patent_app_type] => new [patent_app_number] => 10/059186 [patent_app_country] => US [patent_app_date] => 2002-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5065 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0100/20020100934.pdf [firstpage_image] =>[orig_patent_app_number] => 10059186 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6785735 [patent_doc_number] => 20030136974 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-24 [patent_title] => 'Thick buffer region design to improve IGBT self-clamped inductive switching (SCIS) energy density and device manufacturability' [patent_app_type] => new [patent_app_number] => 10/050976 [patent_app_country] => US [patent_app_date] => 2002-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3800 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20030136974.pdf [firstpage_image] =>[orig_patent_app_number] => 10050976 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6758827 [patent_doc_number] => 20030122188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-03 [patent_title] => 'High voltage power MOSFET having a voltage sustaining region that includes doped columns formed by trench etching and ion implantation' [patent_app_type] => new [patent_app_number] => 10/038845 [patent_app_country] => US [patent_app_date] => 2001-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3455 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20030122188.pdf [firstpage_image] =>[orig_patent_app_number] => 10038845 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1182046 [patent_doc_number] => 06740926 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-25 [patent_title] => 'Planar transistor structure using isolation implants for improved Vss resistance and for process simplification' [patent_app_type] => B1 [patent_app_number] => 10/032646 [patent_app_country] => US [patent_app_date] => 2001-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 1918 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/740/06740926.pdf [firstpage_image] =>[orig_patent_app_number] => 10032646 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6284990 [patent_doc_number] => 20020053711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-09 [patent_title] => 'Device structure and method for reducing silicide encroachment' [patent_app_type] => new [patent_app_number] => 10/010525 [patent_app_country] => US [patent_app_date] => 2001-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4879 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20020053711.pdf [firstpage_image] =>[orig_patent_app_number] => 10010525 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7634361 [patent_doc_number] => 06657259 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-02 [patent_title] => 'Multiple-plane FinFET CMOS' [patent_app_type] => B2 [patent_app_number] => 10/011846 [patent_app_country] => US [patent_app_date] => 2001-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 7498 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/657/06657259.pdf [firstpage_image] =>[orig_patent_app_number] => 10011846 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6577871 [patent_doc_number] => 20020041029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-11 [patent_title] => 'Semiconductor structure including metal nitride and metal silicide' [patent_app_type] => new [patent_app_number] => 10/005439 [patent_app_country] => US [patent_app_date] => 2001-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6177 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20020041029.pdf [firstpage_image] =>[orig_patent_app_number] => 10005439 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7632726 [patent_doc_number] => 06664608 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-16 [patent_title] => 'Back-biased MOS device' [patent_app_type] => B1 [patent_app_number] => 09/996705 [patent_app_country] => US [patent_app_date] => 2001-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 5361 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/664/06664608.pdf [firstpage_image] =>[orig_patent_app_number] => 09996705 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6748020 [patent_doc_number] => 20030042540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-06 [patent_title] => 'Source-down power transistor' [patent_app_type] => new [patent_app_number] => 10/017635 [patent_app_country] => US [patent_app_date] => 2001-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2125 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20030042540.pdf [firstpage_image] =>[orig_patent_app_number] => 10017635 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6799460 [patent_doc_number] => 20030094624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-22 [patent_title] => 'Trench MOSFET device with improved on-resistance' [patent_app_type] => new [patent_app_number] => 09/999116 [patent_app_country] => US [patent_app_date] => 2001-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3667 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20030094624.pdf [firstpage_image] =>[orig_patent_app_number] => 09999116 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1261412 [patent_doc_number] => 06664143 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-16 [patent_title] => 'Methods of fabricating vertical field effect transistors by conformal channel layer deposition on sidewalls' [patent_app_type] => B2 [patent_app_number] => 10/007895 [patent_app_country] => US [patent_app_date] => 2001-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 15 [patent_no_of_words] => 6708 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/664/06664143.pdf [firstpage_image] =>[orig_patent_app_number] => 10007895 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6867706 [patent_doc_number] => 20030080395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-01 [patent_title] => 'Sealed nitride layer for integrated circuits' [patent_app_type] => new [patent_app_number] => 10/033156 [patent_app_country] => US [patent_app_date] => 2001-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3574 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20030080395.pdf [firstpage_image] =>[orig_patent_app_number] => 10033156 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7302963 [patent_doc_number] => 20040114940 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-17 [patent_title] => 'Optical wireless communications' [patent_app_type] => new [patent_app_number] => 10/399326 [patent_app_country] => US [patent_app_date] => 2003-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 5498 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 19 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0114/20040114940.pdf [firstpage_image] =>[orig_patent_app_number] => 10399326 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1207033 [patent_doc_number] => 06717211 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-06 [patent_title] => 'Shallow doped junctions with a variable profile gradation of dopants' [patent_app_type] => B2 [patent_app_number] => 09/981549 [patent_app_country] => US [patent_app_date] => 2001-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3854 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/717/06717211.pdf [firstpage_image] =>[orig_patent_app_number] => 09981549 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6153851 [patent_doc_number] => 20020145170 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-10 [patent_title] => 'Power MOS transistor' [patent_app_type] => new [patent_app_number] => 09/956460 [patent_app_country] => US [patent_app_date] => 2001-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7251 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20020145170.pdf [firstpage_image] =>[orig_patent_app_number] => 09956460 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1321354 [patent_doc_number] => 06605830 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-12 [patent_title] => 'Power semiconductor device including an IGBT with a MOS transistor as a current suppressing device incorporated therein' [patent_app_type] => B1 [patent_app_number] => 09/956125 [patent_app_country] => US [patent_app_date] => 2001-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 18331 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/605/06605830.pdf [firstpage_image] =>[orig_patent_app_number] => 09956125 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7411611 [patent_doc_number] => 20040207020 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-21 [patent_title] => 'CMOS silicon-control-rectifier (SCR) structure for electrostatic discharge (ESD) protection' [patent_app_type] => new [patent_app_number] => 09/952125 [patent_app_country] => US [patent_app_date] => 2001-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3902 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0207/20040207020.pdf [firstpage_image] =>[orig_patent_app_number] => 09952125 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1086488 [patent_doc_number] => 06831331 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-14 [patent_title] => 'Power MOS transistor for absorbing surge current' [patent_app_type] => B2 [patent_app_number] => 09/945621 [patent_app_country] => US [patent_app_date] => 2001-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 60 [patent_no_of_words] => 15536 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/831/06831331.pdf [firstpage_image] =>[orig_patent_app_number] => 09945621 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6718677 [patent_doc_number] => 20030052364 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-20 [patent_title] => 'Vertical dual gate field effect transistor' [patent_app_type] => new [patent_app_number] => 09/944665 [patent_app_country] => US [patent_app_date] => 2001-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 40 [patent_no_of_words] => 5535 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20030052364.pdf [firstpage_image] =>[orig_patent_app_number] => 09944665 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6476034 [patent_doc_number] => 20020024090 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-28 [patent_title] => '3-D smart power IC' [patent_app_type] => new [patent_app_number] => 09/797165 [patent_app_country] => US [patent_app_date] => 2001-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2853 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20020024090.pdf [firstpage_image] =>[orig_patent_app_number] => 09797165 [rel_patent_id] =>[rel_patent_doc_number] =>)