Search

Devon C. Kramer

Supervisory Patent Examiner (ID: 1983, Phone: (571)272-7118 , Office: P/3746 )

Most Active Art Unit
3683
Art Unit(s)
3683, 3741, 3613, 3746
Total Applications
1035
Issued Applications
672
Pending Applications
81
Abandoned Applications
283

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 677114 [patent_doc_number] => 07087975 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-08 [patent_title] => 'Area efficient stacking of antifuses in semiconductor device' [patent_app_type] => utility [patent_app_number] => 09/751474 [patent_app_country] => US [patent_app_date] => 2000-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 13179 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/087/07087975.pdf [firstpage_image] =>[orig_patent_app_number] => 09751474 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/751474
Area efficient stacking of antifuses in semiconductor device Dec 27, 2000 Issued
Array ( [id] => 1459816 [patent_doc_number] => 06426517 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-07-30 [patent_title] => 'Active matrix display device having multiple gate electrode portions' [patent_app_type] => B2 [patent_app_number] => 09/736139 [patent_app_country] => US [patent_app_date] => 2000-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 4325 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/426/06426517.pdf [firstpage_image] =>[orig_patent_app_number] => 09736139 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/736139
Active matrix display device having multiple gate electrode portions Dec 12, 2000 Issued
Array ( [id] => 951595 [patent_doc_number] => 06960800 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-01 [patent_title] => 'Semiconductor device and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 09/734176 [patent_app_country] => US [patent_app_date] => 2000-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4312 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/960/06960800.pdf [firstpage_image] =>[orig_patent_app_number] => 09734176 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/734176
Semiconductor device and method for fabricating the same Dec 11, 2000 Issued
Array ( [id] => 6875527 [patent_doc_number] => 20010000620 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-05-03 [patent_title] => 'Thin film transistor and method of fabricating the same' [patent_app_type] => new-utility [patent_app_number] => 09/730875 [patent_app_country] => US [patent_app_date] => 2000-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6395 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0000/20010000620.pdf [firstpage_image] =>[orig_patent_app_number] => 09730875 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/730875
Thin film transistor and method of fabricating the same Dec 4, 2000 Abandoned
Array ( [id] => 1422288 [patent_doc_number] => 06518623 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-11 [patent_title] => 'Semiconductor device having a buried-channel MOS structure' [patent_app_type] => B1 [patent_app_number] => 09/718486 [patent_app_country] => US [patent_app_date] => 2000-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 36 [patent_no_of_words] => 8595 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/518/06518623.pdf [firstpage_image] =>[orig_patent_app_number] => 09718486 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/718486
Semiconductor device having a buried-channel MOS structure Nov 23, 2000 Issued
09/716306 Self-align offset gate structure and method of manufacture Nov 19, 2000 Abandoned
Array ( [id] => 1302478 [patent_doc_number] => 06624493 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-23 [patent_title] => 'Biasing, operation and parasitic current limitation in single device equivalent to CMOS, and other semiconductor systems' [patent_app_type] => B1 [patent_app_number] => 09/716046 [patent_app_country] => US [patent_app_date] => 2000-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 31 [patent_no_of_words] => 21495 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 338 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/624/06624493.pdf [firstpage_image] =>[orig_patent_app_number] => 09716046 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/716046
Biasing, operation and parasitic current limitation in single device equivalent to CMOS, and other semiconductor systems Nov 19, 2000 Issued
Array ( [id] => 7634340 [patent_doc_number] => 06657280 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-02 [patent_title] => 'Redundant interconnect high current bipolar device' [patent_app_type] => B1 [patent_app_number] => 09/711726 [patent_app_country] => US [patent_app_date] => 2000-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3535 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/657/06657280.pdf [firstpage_image] =>[orig_patent_app_number] => 09711726 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/711726
Redundant interconnect high current bipolar device Nov 12, 2000 Issued
Array ( [id] => 1229935 [patent_doc_number] => 06696722 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-24 [patent_title] => 'Storage node of DRAM cell' [patent_app_type] => B1 [patent_app_number] => 09/708957 [patent_app_country] => US [patent_app_date] => 2000-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2266 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/696/06696722.pdf [firstpage_image] =>[orig_patent_app_number] => 09708957 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/708957
Storage node of DRAM cell Nov 7, 2000 Issued
Array ( [id] => 1383913 [patent_doc_number] => 06559475 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Test pattern for evaluating a process of silicide film formation' [patent_app_type] => B1 [patent_app_number] => 09/704760 [patent_app_country] => US [patent_app_date] => 2000-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3738 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/559/06559475.pdf [firstpage_image] =>[orig_patent_app_number] => 09704760 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/704760
Test pattern for evaluating a process of silicide film formation Nov 2, 2000 Issued
Array ( [id] => 1424221 [patent_doc_number] => 06507071 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-14 [patent_title] => 'Lateral high-voltage sidewall transistor' [patent_app_type] => B1 [patent_app_number] => 09/694435 [patent_app_country] => US [patent_app_date] => 2000-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2498 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/507/06507071.pdf [firstpage_image] =>[orig_patent_app_number] => 09694435 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/694435
Lateral high-voltage sidewall transistor Oct 22, 2000 Issued
Array ( [id] => 1375483 [patent_doc_number] => 06558996 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Edge structure for relaxing electric field of semiconductor device having an embedded type diffusion structure' [patent_app_type] => B1 [patent_app_number] => 09/691016 [patent_app_country] => US [patent_app_date] => 2000-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4882 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 321 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/558/06558996.pdf [firstpage_image] =>[orig_patent_app_number] => 09691016 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/691016
Edge structure for relaxing electric field of semiconductor device having an embedded type diffusion structure Oct 17, 2000 Issued
Array ( [id] => 1302274 [patent_doc_number] => 06624469 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-23 [patent_title] => 'Vertical MOS transistor having body region formed by inclined ion implantation' [patent_app_type] => B1 [patent_app_number] => 09/690226 [patent_app_country] => US [patent_app_date] => 2000-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 5866 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/624/06624469.pdf [firstpage_image] =>[orig_patent_app_number] => 09690226 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/690226
Vertical MOS transistor having body region formed by inclined ion implantation Oct 16, 2000 Issued
Array ( [id] => 1299941 [patent_doc_number] => 06627925 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-30 [patent_title] => 'Transistor having a novel layout and an emitter having more than one feed point' [patent_app_type] => B1 [patent_app_number] => 09/687381 [patent_app_country] => US [patent_app_date] => 2000-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 48 [patent_no_of_words] => 7909 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/627/06627925.pdf [firstpage_image] =>[orig_patent_app_number] => 09687381 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/687381
Transistor having a novel layout and an emitter having more than one feed point Oct 12, 2000 Issued
Array ( [id] => 1178472 [patent_doc_number] => 06747313 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-08 [patent_title] => 'Thin film transistor' [patent_app_type] => B1 [patent_app_number] => 09/689746 [patent_app_country] => US [patent_app_date] => 2000-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 1823 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/747/06747313.pdf [firstpage_image] =>[orig_patent_app_number] => 09689746 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/689746
Thin film transistor Oct 12, 2000 Issued
Array ( [id] => 1390505 [patent_doc_number] => 06552361 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Thin film transistor device' [patent_app_type] => B1 [patent_app_number] => 09/680935 [patent_app_country] => US [patent_app_date] => 2000-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 1984 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/552/06552361.pdf [firstpage_image] =>[orig_patent_app_number] => 09680935 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/680935
Thin film transistor device Oct 9, 2000 Issued
Array ( [id] => 1576285 [patent_doc_number] => 06469343 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-22 [patent_title] => 'Multi-level type nonvolatile semiconductor memory device' [patent_app_type] => B1 [patent_app_number] => 09/679650 [patent_app_country] => US [patent_app_date] => 2000-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 10631 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/469/06469343.pdf [firstpage_image] =>[orig_patent_app_number] => 09679650 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/679650
Multi-level type nonvolatile semiconductor memory device Oct 4, 2000 Issued
Array ( [id] => 1272821 [patent_doc_number] => 06653699 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-25 [patent_title] => 'Polysilicon/Amorphous silicon gate structures for integrated circuit field effect transistors' [patent_app_type] => B1 [patent_app_number] => 09/672436 [patent_app_country] => US [patent_app_date] => 2000-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 4217 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/653/06653699.pdf [firstpage_image] =>[orig_patent_app_number] => 09672436 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/672436
Polysilicon/Amorphous silicon gate structures for integrated circuit field effect transistors Sep 27, 2000 Issued
Array ( [id] => 1386345 [patent_doc_number] => 06555862 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-29 [patent_title] => 'Self-aligned buried strap for vertical transistors' [patent_app_type] => B1 [patent_app_number] => 09/670745 [patent_app_country] => US [patent_app_date] => 2000-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 3737 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/555/06555862.pdf [firstpage_image] =>[orig_patent_app_number] => 09670745 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/670745
Self-aligned buried strap for vertical transistors Sep 26, 2000 Issued
Array ( [id] => 1136369 [patent_doc_number] => 06784490 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-31 [patent_title] => 'High-voltage MOS transistor' [patent_app_type] => B1 [patent_app_number] => 09/666156 [patent_app_country] => US [patent_app_date] => 2000-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 28 [patent_no_of_words] => 11090 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/784/06784490.pdf [firstpage_image] =>[orig_patent_app_number] => 09666156 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/666156
High-voltage MOS transistor Sep 18, 2000 Issued
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