Search

Devon C. Kramer

Supervisory Patent Examiner (ID: 1983, Phone: (571)272-7118 , Office: P/3746 )

Most Active Art Unit
3683
Art Unit(s)
3683, 3741, 3613, 3746
Total Applications
1035
Issued Applications
672
Pending Applications
81
Abandoned Applications
283

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7639806 [patent_doc_number] => 06396110 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Semiconductor device with multiple emitter contact plugs' [patent_app_type] => B1 [patent_app_number] => 09/514385 [patent_app_country] => US [patent_app_date] => 2000-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3281 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/396/06396110.pdf [firstpage_image] =>[orig_patent_app_number] => 09514385 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/514385
Semiconductor device with multiple emitter contact plugs Feb 27, 2000 Issued
Array ( [id] => 4276767 [patent_doc_number] => 06246075 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Test structures for monitoring gate oxide defect densities and the plasma antenna effect' [patent_app_type] => 1 [patent_app_number] => 9/507883 [patent_app_country] => US [patent_app_date] => 2000-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 3360 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/246/06246075.pdf [firstpage_image] =>[orig_patent_app_number] => 507883 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/507883
Test structures for monitoring gate oxide defect densities and the plasma antenna effect Feb 21, 2000 Issued
Array ( [id] => 1505389 [patent_doc_number] => 06465845 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Smart power device and method for fabricating the same' [patent_app_type] => B1 [patent_app_number] => 09/500575 [patent_app_country] => US [patent_app_date] => 2000-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 27 [patent_no_of_words] => 3715 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/465/06465845.pdf [firstpage_image] =>[orig_patent_app_number] => 09500575 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/500575
Smart power device and method for fabricating the same Feb 9, 2000 Issued
Array ( [id] => 1328203 [patent_doc_number] => 06603185 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-05 [patent_title] => 'Voltage withstanding structure for a semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/494995 [patent_app_country] => US [patent_app_date] => 2000-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 7267 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/603/06603185.pdf [firstpage_image] =>[orig_patent_app_number] => 09494995 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/494995
Voltage withstanding structure for a semiconductor device Jan 30, 2000 Issued
Array ( [id] => 1576290 [patent_doc_number] => 06469344 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-10-22 [patent_title] => 'Semiconductor device having low on resistance high speed turn off and short switching turn off storage time' [patent_app_type] => B2 [patent_app_number] => 09/461264 [patent_app_country] => US [patent_app_date] => 1999-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 6860 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/469/06469344.pdf [firstpage_image] =>[orig_patent_app_number] => 09461264 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/461264
Semiconductor device having low on resistance high speed turn off and short switching turn off storage time Dec 14, 1999 Issued
Array ( [id] => 1249084 [patent_doc_number] => 06674107 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-06 [patent_title] => 'Enhancement mode junction field effect transistor with low on resistance' [patent_app_type] => B1 [patent_app_number] => 09/453136 [patent_app_country] => US [patent_app_date] => 1999-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2241 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/674/06674107.pdf [firstpage_image] =>[orig_patent_app_number] => 09453136 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/453136
Enhancement mode junction field effect transistor with low on resistance Dec 1, 1999 Issued
Array ( [id] => 7647087 [patent_doc_number] => 06476431 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-05 [patent_title] => 'Field effect transistor with barrier layer to prevent avalanche breakdown current from reaching gate and method for manufacturing the same' [patent_app_type] => B1 [patent_app_number] => 09/438840 [patent_app_country] => US [patent_app_date] => 1999-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 7278 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/476/06476431.pdf [firstpage_image] =>[orig_patent_app_number] => 09438840 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/438840
Field effect transistor with barrier layer to prevent avalanche breakdown current from reaching gate and method for manufacturing the same Nov 11, 1999 Issued
Array ( [id] => 1056845 [patent_doc_number] => 06855983 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-15 [patent_title] => 'Semiconductor device having reduced on resistance' [patent_app_type] => utility [patent_app_number] => 09/435766 [patent_app_country] => US [patent_app_date] => 1999-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 22 [patent_no_of_words] => 4655 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/855/06855983.pdf [firstpage_image] =>[orig_patent_app_number] => 09435766 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/435766
Semiconductor device having reduced on resistance Nov 7, 1999 Issued
Array ( [id] => 1002657 [patent_doc_number] => 06909114 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-06-21 [patent_title] => 'Semiconductor device having LDD regions' [patent_app_type] => utility [patent_app_number] => 09/433705 [patent_app_country] => US [patent_app_date] => 1999-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 120 [patent_no_of_words] => 25696 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/909/06909114.pdf [firstpage_image] =>[orig_patent_app_number] => 09433705 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/433705
Semiconductor device having LDD regions Nov 3, 1999 Issued
Array ( [id] => 4277193 [patent_doc_number] => 06246103 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Bipolar junction transistor with tunneling current through the gate of a field effect transistor as base current' [patent_app_type] => 1 [patent_app_number] => 9/427136 [patent_app_country] => US [patent_app_date] => 1999-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3500 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/246/06246103.pdf [firstpage_image] =>[orig_patent_app_number] => 427136 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/427136
Bipolar junction transistor with tunneling current through the gate of a field effect transistor as base current Oct 24, 1999 Issued
Array ( [id] => 1374809 [patent_doc_number] => 06566732 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-20 [patent_title] => 'High voltage resistive structure integrated on a semiconductor substrate' [patent_app_type] => B1 [patent_app_number] => 09/425445 [patent_app_country] => US [patent_app_date] => 1999-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 13 [patent_no_of_words] => 3077 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/566/06566732.pdf [firstpage_image] =>[orig_patent_app_number] => 09425445 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/425445
High voltage resistive structure integrated on a semiconductor substrate Oct 21, 1999 Issued
Array ( [id] => 7626594 [patent_doc_number] => 06768168 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-27 [patent_title] => 'Insulated gate semiconductor device with low on voltage and manufacturing method thereof' [patent_app_type] => B1 [patent_app_number] => 09/421217 [patent_app_country] => US [patent_app_date] => 1999-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 31 [patent_no_of_words] => 11965 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 7 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/768/06768168.pdf [firstpage_image] =>[orig_patent_app_number] => 09421217 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/421217
Insulated gate semiconductor device with low on voltage and manufacturing method thereof Oct 19, 1999 Issued
09/421064 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING SAME USING DUMMY PATTERNS TO PLANARIZE OVERLYING LAYERS Oct 18, 1999 Abandoned
Array ( [id] => 4360645 [patent_doc_number] => 06218706 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Integrated circuit with improved electrostatic discharge protection circuitry' [patent_app_type] => 1 [patent_app_number] => 9/418850 [patent_app_country] => US [patent_app_date] => 1999-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 6772 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218706.pdf [firstpage_image] =>[orig_patent_app_number] => 418850 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/418850
Integrated circuit with improved electrostatic discharge protection circuitry Oct 14, 1999 Issued
Array ( [id] => 1116856 [patent_doc_number] => 06800875 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-05 [patent_title] => 'Active matrix electro-luminescent display device with an organic leveling layer' [patent_app_type] => B1 [patent_app_number] => 09/414906 [patent_app_country] => US [patent_app_date] => 1999-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 3837 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/800/06800875.pdf [firstpage_image] =>[orig_patent_app_number] => 09414906 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/414906
Active matrix electro-luminescent display device with an organic leveling layer Oct 7, 1999 Issued
Array ( [id] => 1509367 [patent_doc_number] => 06441445 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Integrated device with bipolar transistor and electronic switch in emitter switching configuration' [patent_app_type] => B1 [patent_app_number] => 09/413740 [patent_app_country] => US [patent_app_date] => 1999-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3405 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/441/06441445.pdf [firstpage_image] =>[orig_patent_app_number] => 09413740 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/413740
Integrated device with bipolar transistor and electronic switch in emitter switching configuration Oct 5, 1999 Issued
Array ( [id] => 1486702 [patent_doc_number] => 06365931 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Gate insulating structure for power devices, and related manufacturing process' [patent_app_type] => B1 [patent_app_number] => 09/412475 [patent_app_country] => US [patent_app_date] => 1999-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2414 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/365/06365931.pdf [firstpage_image] =>[orig_patent_app_number] => 09412475 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/412475
Gate insulating structure for power devices, and related manufacturing process Oct 4, 1999 Issued
Array ( [id] => 4350720 [patent_doc_number] => 06285046 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Controllable semiconductor structure with improved switching properties' [patent_app_type] => 1 [patent_app_number] => 9/297304 [patent_app_country] => US [patent_app_date] => 1999-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3306 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/285/06285046.pdf [firstpage_image] =>[orig_patent_app_number] => 297304 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/297304
Controllable semiconductor structure with improved switching properties Oct 3, 1999 Issued
Array ( [id] => 4254552 [patent_doc_number] => 06222233 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Lateral RF MOS device with improved drain structure' [patent_app_type] => 1 [patent_app_number] => 9/410934 [patent_app_country] => US [patent_app_date] => 1999-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5801 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 340 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/222/06222233.pdf [firstpage_image] =>[orig_patent_app_number] => 410934 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/410934
Lateral RF MOS device with improved drain structure Oct 3, 1999 Issued
Array ( [id] => 1189936 [patent_doc_number] => 06734523 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-11 [patent_title] => 'Semiconductor device including a well divided into a plurality of parts by a trench' [patent_app_type] => B2 [patent_app_number] => 09/395184 [patent_app_country] => US [patent_app_date] => 1999-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 45 [patent_no_of_words] => 8317 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/734/06734523.pdf [firstpage_image] =>[orig_patent_app_number] => 09395184 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/395184
Semiconductor device including a well divided into a plurality of parts by a trench Sep 13, 1999 Issued
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