Devon C. Kramer

Array ( [id] => 4158769 [patent_doc_number] => 06124607 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Capacitive memory cell' [patent_app_type] => 1 [patent_app_number] => 9/096006 [patent_app_country] => US [patent_app_date] => 1998-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4074 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/124/06124607.pdf [firstpage_image] =>[orig_patent_app_number] => 096006 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1518716 [patent_doc_number] => 06501094 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-31 [patent_title] => 'Semiconductor device comprising a bottom gate type thin film transistor' [patent_app_type] => B1 [patent_app_number] => 09/095026 [patent_app_country] => US [patent_app_date] => 1998-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 41 [patent_no_of_words] => 7631 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/501/06501094.pdf [firstpage_image] =>[orig_patent_app_number] => 09095026 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1116968 [patent_doc_number] => 06800928 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-05 [patent_title] => 'Porous integrated circuit dielectric with decreased surface porosity' [patent_app_type] => B1 [patent_app_number] => 09/087234 [patent_app_country] => US [patent_app_date] => 1998-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 27 [patent_no_of_words] => 5238 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/800/06800928.pdf [firstpage_image] =>[orig_patent_app_number] => 09087234 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4183765 [patent_doc_number] => 06037615 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Metal semiconductor FET having doped A1GaAs layer between channel layer and A1GaAs buffer layer' [patent_app_type] => 1 [patent_app_number] => 9/083934 [patent_app_country] => US [patent_app_date] => 1998-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2816 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/037/06037615.pdf [firstpage_image] =>[orig_patent_app_number] => 083934 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4186889 [patent_doc_number] => 06020603 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'Semiconductor device with a beveled and chamfered outer peripheral portion' [patent_app_type] => 1 [patent_app_number] => 9/068974 [patent_app_country] => US [patent_app_date] => 1998-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3848 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/020/06020603.pdf [firstpage_image] =>[orig_patent_app_number] => 068974 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4091114 [patent_doc_number] => 06025652 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Semiconductor device and method of producing same' [patent_app_type] => 1 [patent_app_number] => 9/081680 [patent_app_country] => US [patent_app_date] => 1998-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 55 [patent_no_of_words] => 9015 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/025/06025652.pdf [firstpage_image] =>[orig_patent_app_number] => 081680 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1544294 [patent_doc_number] => 06373113 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Nitrogenated gate structure for improved transistor performance and method for making same' [patent_app_type] => B1 [patent_app_number] => 09/073755 [patent_app_country] => US [patent_app_date] => 1998-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3824 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/373/06373113.pdf [firstpage_image] =>[orig_patent_app_number] => 09073755 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4340922 [patent_doc_number] => 06333528 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-25 [patent_title] => 'Semiconductor device having a capacitor exhibiting improved moisture resistance' [patent_app_type] => 1 [patent_app_number] => 9/071795 [patent_app_country] => US [patent_app_date] => 1998-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 28 [patent_no_of_words] => 7109 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/333/06333528.pdf [firstpage_image] =>[orig_patent_app_number] => 071795 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4366377 [patent_doc_number] => 06255710 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => '3-D smart power IC' [patent_app_type] => 1 [patent_app_number] => 9/072339 [patent_app_country] => US [patent_app_date] => 1998-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2877 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/255/06255710.pdf [firstpage_image] =>[orig_patent_app_number] => 072339 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4363466 [patent_doc_number] => 06169304 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Semiconductor device having a passivation layer which minimizes diffusion of hydrogen into a dielectric layer' [patent_app_type] => 1 [patent_app_number] => 9/071534 [patent_app_country] => US [patent_app_date] => 1998-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 28 [patent_no_of_words] => 7106 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/169/06169304.pdf [firstpage_image] =>[orig_patent_app_number] => 071534 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4194990 [patent_doc_number] => 06153915 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'CMOS semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/070915 [patent_app_country] => US [patent_app_date] => 1998-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 4081 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/153/06153915.pdf [firstpage_image] =>[orig_patent_app_number] => 070915 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4366257 [patent_doc_number] => 06255701 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Semiconductor device containing local interconnection and method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/070235 [patent_app_country] => US [patent_app_date] => 1998-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 6676 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/255/06255701.pdf [firstpage_image] =>[orig_patent_app_number] => 070235 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4222453 [patent_doc_number] => 06111301 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Interconnection with integrated corrosion stop' [patent_app_type] => 1 [patent_app_number] => 9/066121 [patent_app_country] => US [patent_app_date] => 1998-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1651 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/111/06111301.pdf [firstpage_image] =>[orig_patent_app_number] => 066121 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1197804 [patent_doc_number] => 06727569 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-27 [patent_title] => 'Method of making enhanced trench oxide with low temperature nitrogen integration' [patent_app_type] => B1 [patent_app_number] => 09/063081 [patent_app_country] => US [patent_app_date] => 1998-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 3031 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 16 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/727/06727569.pdf [firstpage_image] =>[orig_patent_app_number] => 09063081 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5782870 [patent_doc_number] => 20020158312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-31 [patent_title] => 'DEVICES WITH PATTERNED WELLS AND METHOD FOR FORMING SAME' [patent_app_type] => new [patent_app_number] => 09/062964 [patent_app_country] => US [patent_app_date] => 1998-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4146 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 20 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20020158312.pdf [firstpage_image] =>[orig_patent_app_number] => 09062964 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4196184 [patent_doc_number] => 06130447 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-10 [patent_title] => 'Integrated circuit memories and power distribution methods including at least two control lines between adjacent power lines' [patent_app_type] => 1 [patent_app_number] => 9/061390 [patent_app_country] => US [patent_app_date] => 1998-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 1965 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/130/06130447.pdf [firstpage_image] =>[orig_patent_app_number] => 061390 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4089455 [patent_doc_number] => 06163048 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Semiconductor non-volatile memory device having a NAND cell structure' [patent_app_type] => 1 [patent_app_number] => 9/051700 [patent_app_country] => US [patent_app_date] => 1998-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 10472 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/163/06163048.pdf [firstpage_image] =>[orig_patent_app_number] => 051700 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5918018 [patent_doc_number] => 20020113278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-22 [patent_title] => 'STACKED SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => new [patent_app_number] => 09/052065 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6132 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20020113278.pdf [firstpage_image] =>[orig_patent_app_number] => 09052065 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4197455 [patent_doc_number] => 06043534 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'High voltage semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/052142 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 6944 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/043/06043534.pdf [firstpage_image] =>[orig_patent_app_number] => 052142 [rel_patent_id] =>[rel_patent_doc_number] =>)