Devon C. Kramer

Array ( [id] => 4108441 [patent_doc_number] => 06100572 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Amorphous silicon combined with resurf region for termination for MOSgated device' [patent_app_type] => 1 [patent_app_number] => 8/822398 [patent_app_country] => US [patent_app_date] => 1997-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2856 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 318 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/100/06100572.pdf [firstpage_image] =>[orig_patent_app_number] => 822398 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3953734 [patent_doc_number] => 05977591 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'High-voltage-resistant MOS transistor, and corresponding manufacturing process' [patent_app_type] => 1 [patent_app_number] => 8/824888 [patent_app_country] => US [patent_app_date] => 1997-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 6150 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 322 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/977/05977591.pdf [firstpage_image] =>[orig_patent_app_number] => 824888 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4297576 [patent_doc_number] => 06236099 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Trench MOS device and process for radhard device' [patent_app_type] => 1 [patent_app_number] => 8/818908 [patent_app_country] => US [patent_app_date] => 1997-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2581 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/236/06236099.pdf [firstpage_image] =>[orig_patent_app_number] => 818908 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3799553 [patent_doc_number] => 05780907 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'Semiconductor device having triple wells' [patent_app_type] => 1 [patent_app_number] => 8/819488 [patent_app_country] => US [patent_app_date] => 1997-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 43 [patent_no_of_words] => 9080 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/780/05780907.pdf [firstpage_image] =>[orig_patent_app_number] => 819488 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3985188 [patent_doc_number] => 05949133 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Semiconductor interconnect structure for high temperature applications' [patent_app_type] => 1 [patent_app_number] => 8/815546 [patent_app_country] => US [patent_app_date] => 1997-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 2647 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/949/05949133.pdf [firstpage_image] =>[orig_patent_app_number] => 815546 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3880253 [patent_doc_number] => 05825077 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-20 [patent_title] => 'Interconnect decoupling scheme' [patent_app_type] => 1 [patent_app_number] => 8/815764 [patent_app_country] => US [patent_app_date] => 1997-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3063 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/825/05825077.pdf [firstpage_image] =>[orig_patent_app_number] => 815764 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3896032 [patent_doc_number] => 05834816 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'MOSFET having tapered gate electrode' [patent_app_type] => 1 [patent_app_number] => 8/816009 [patent_app_country] => US [patent_app_date] => 1997-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 1781 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/834/05834816.pdf [firstpage_image] =>[orig_patent_app_number] => 816009 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4212135 [patent_doc_number] => 06028324 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Test structures for monitoring gate oxide defect densities and the plasma antenna effect' [patent_app_type] => 1 [patent_app_number] => 8/813758 [patent_app_country] => US [patent_app_date] => 1997-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 3821 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/028/06028324.pdf [firstpage_image] =>[orig_patent_app_number] => 813758 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4136943 [patent_doc_number] => 06034399 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Electrostatic discharge protection for silicon-on-insulator' [patent_app_type] => 1 [patent_app_number] => 8/812183 [patent_app_country] => US [patent_app_date] => 1997-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1656 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/034/06034399.pdf [firstpage_image] =>[orig_patent_app_number] => 812183 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4026760 [patent_doc_number] => 05925895 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Silicon carbide power MESFET with surface effect supressive layer' [patent_app_type] => 1 [patent_app_number] => 8/812227 [patent_app_country] => US [patent_app_date] => 1997-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4233 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/925/05925895.pdf [firstpage_image] =>[orig_patent_app_number] => 812227 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1509402 [patent_doc_number] => 06441455 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Low dosage field rings for high voltage semiconductor device' [patent_app_type] => B1 [patent_app_number] => 08/812848 [patent_app_country] => US [patent_app_date] => 1997-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1584 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/441/06441455.pdf [firstpage_image] =>[orig_patent_app_number] => 08812848 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1587739 [patent_doc_number] => 06359294 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Insulator-compound semiconductor interface structure' [patent_app_type] => B1 [patent_app_number] => 08/812952 [patent_app_country] => US [patent_app_date] => 1997-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 3207 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/359/06359294.pdf [firstpage_image] =>[orig_patent_app_number] => 08812952 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4413999 [patent_doc_number] => 06265738 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Thin film ferroelectric capacitors having improved memory retention through the use of essentially smooth bottom electrode structures' [patent_app_type] => 1 [patent_app_number] => 8/810538 [patent_app_country] => US [patent_app_date] => 1997-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 11048 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/265/06265738.pdf [firstpage_image] =>[orig_patent_app_number] => 810538 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7040032 [patent_doc_number] => 20010005035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-06-28 [patent_title] => 'BIPOLAR TRANSISTOR HAVING LIGHTLY DOPED EPITAXIAL COLLECTOR REGION CONSTANT IN DOPANT IMPURITY AND PROCESS OF FABRICATION THEREOF' [patent_app_type] => new-utility [patent_app_number] => 08/807326 [patent_app_country] => US [patent_app_date] => 1997-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5896 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20010005035.pdf [firstpage_image] =>[orig_patent_app_number] => 08807326 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3961119 [patent_doc_number] => 05936286 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Differential poly-edge oxidation for stable SRAM cells' [patent_app_type] => 1 [patent_app_number] => 8/806346 [patent_app_country] => US [patent_app_date] => 1997-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4897 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/936/05936286.pdf [firstpage_image] =>[orig_patent_app_number] => 806346 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4300939 [patent_doc_number] => 06198117 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Transistor having main cell and sub-cells' [patent_app_type] => 1 [patent_app_number] => 8/806422 [patent_app_country] => US [patent_app_date] => 1997-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 4397 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/198/06198117.pdf [firstpage_image] =>[orig_patent_app_number] => 806422 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4227616 [patent_doc_number] => 06011291 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-04 [patent_title] => 'Video display with integrated control circuitry formed on a dielectric substrate' [patent_app_type] => 1 [patent_app_number] => 8/803933 [patent_app_country] => US [patent_app_date] => 1997-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 2275 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/011/06011291.pdf [firstpage_image] =>[orig_patent_app_number] => 803933 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4120072 [patent_doc_number] => 06046491 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-04 [patent_title] => 'Semiconductor resistor element having improved resistance tolerance and semiconductor device therefor' [patent_app_type] => 1 [patent_app_number] => 8/802314 [patent_app_country] => US [patent_app_date] => 1997-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8863 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 340 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/046/06046491.pdf [firstpage_image] =>[orig_patent_app_number] => 802314 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3820554 [patent_doc_number] => 05789782 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-04 [patent_title] => 'Lateral semiconductor device with maximized breakdown voltage, and methods of fixing potential of same' [patent_app_type] => 1 [patent_app_number] => 8/794146 [patent_app_country] => US [patent_app_date] => 1997-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4076 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/789/05789782.pdf [firstpage_image] =>[orig_patent_app_number] => 794146 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3984840 [patent_doc_number] => 05949109 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Semiconductor device having input protection circuit' [patent_app_type] => 1 [patent_app_number] => 8/790804 [patent_app_country] => US [patent_app_date] => 1997-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 4527 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/949/05949109.pdf [firstpage_image] =>[orig_patent_app_number] => 790804 [rel_patent_id] =>[rel_patent_doc_number] =>)