Search

Devon C. Kramer

Supervisory Patent Examiner (ID: 1983, Phone: (571)272-7118 , Office: P/3746 )

Most Active Art Unit
3683
Art Unit(s)
3683, 3741, 3613, 3746
Total Applications
1035
Issued Applications
672
Pending Applications
81
Abandoned Applications
283

Applications

Application numberTitle of the applicationFiling DateStatus
08/622782 EXTERNAL STORAGE DEVICE AND EXTERNAL STORAGE DEVICE UNIT AND METHOD OF PRODUCING EXTERNAL STORAGE DEVICE Mar 26, 1996 Abandoned
Array ( [id] => 3781913 [patent_doc_number] => 05818077 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Field effect transistor including a plurality of electrode units arranged in a row' [patent_app_type] => 1 [patent_app_number] => 8/621602 [patent_app_country] => US [patent_app_date] => 1996-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5168 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/818/05818077.pdf [firstpage_image] =>[orig_patent_app_number] => 621602 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/621602
Field effect transistor including a plurality of electrode units arranged in a row Mar 25, 1996 Issued
Array ( [id] => 4027013 [patent_doc_number] => 05925912 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Semiconductor apparatus having a conductive sidewall structure' [patent_app_type] => 1 [patent_app_number] => 8/622108 [patent_app_country] => US [patent_app_date] => 1996-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 36 [patent_no_of_words] => 7778 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/925/05925912.pdf [firstpage_image] =>[orig_patent_app_number] => 622108 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/622108
Semiconductor apparatus having a conductive sidewall structure Mar 25, 1996 Issued
08/621420 REDUCING REVERSE SHORT-CHANNEL EFFECT WITH LIGHT DOSE OF P WITH HIGH DOSE OF AS IN N-CHANNEL LDD Mar 24, 1996 Abandoned
08/620462 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Mar 21, 1996 Abandoned
Array ( [id] => 3865783 [patent_doc_number] => 05796146 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-18 [patent_title] => 'Semiconductor device having a lateral insulated gate biopolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/621758 [patent_app_country] => US [patent_app_date] => 1996-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3260 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/796/05796146.pdf [firstpage_image] =>[orig_patent_app_number] => 621758 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/621758
Semiconductor device having a lateral insulated gate biopolar transistor Mar 21, 1996 Issued
Array ( [id] => 3836940 [patent_doc_number] => 05814864 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-29 [patent_title] => 'Semiconductor circuit including non-ESD transistors with reduced degradation due to an impurity implant' [patent_app_type] => 1 [patent_app_number] => 8/620099 [patent_app_country] => US [patent_app_date] => 1996-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1978 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/814/05814864.pdf [firstpage_image] =>[orig_patent_app_number] => 620099 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/620099
Semiconductor circuit including non-ESD transistors with reduced degradation due to an impurity implant Mar 20, 1996 Issued
Array ( [id] => 3801599 [patent_doc_number] => 05828083 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Array of thin film transistors without a step region at intersection of gate bus and source bus electrodes' [patent_app_type] => 1 [patent_app_number] => 8/616780 [patent_app_country] => US [patent_app_date] => 1996-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 2016 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/828/05828083.pdf [firstpage_image] =>[orig_patent_app_number] => 616780 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/616780
Array of thin film transistors without a step region at intersection of gate bus and source bus electrodes Mar 18, 1996 Issued
Array ( [id] => 3668584 [patent_doc_number] => 05668380 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-16 [patent_title] => 'Reduced area metal contact to a thin polysilicon layer contact structure having low ohmic resistance' [patent_app_type] => 1 [patent_app_number] => 8/612398 [patent_app_country] => US [patent_app_date] => 1996-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 5062 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/668/05668380.pdf [firstpage_image] =>[orig_patent_app_number] => 612398 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/612398
Reduced area metal contact to a thin polysilicon layer contact structure having low ohmic resistance Mar 6, 1996 Issued
Array ( [id] => 4310216 [patent_doc_number] => 06252281 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Semiconductor device having an SOI substrate' [patent_app_type] => 1 [patent_app_number] => 8/612456 [patent_app_country] => US [patent_app_date] => 1996-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 70 [patent_figures_cnt] => 102 [patent_no_of_words] => 39098 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/252/06252281.pdf [firstpage_image] =>[orig_patent_app_number] => 612456 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/612456
Semiconductor device having an SOI substrate Mar 6, 1996 Issued
Array ( [id] => 4137565 [patent_doc_number] => 06147383 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'LDD buried channel field effect semiconductor device and manufacturing method' [patent_app_type] => 1 [patent_app_number] => 8/611188 [patent_app_country] => US [patent_app_date] => 1996-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2565 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 306 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/147/06147383.pdf [firstpage_image] =>[orig_patent_app_number] => 611188 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/611188
LDD buried channel field effect semiconductor device and manufacturing method Mar 4, 1996 Issued
08/610940 POWER MOSFET DEVICE HAVING LOW ON-RESISTANCE AND METHOD Mar 4, 1996 Abandoned
08/610414 SEMICONDUCTOR DEVICE CAPABLE OF AVOIDING DAMAGE BY ESD Mar 3, 1996 Abandoned
Array ( [id] => 3865486 [patent_doc_number] => 05796124 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-18 [patent_title] => 'MOS gate controlled thyristor' [patent_app_type] => 1 [patent_app_number] => 8/610070 [patent_app_country] => US [patent_app_date] => 1996-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 109 [patent_no_of_words] => 20445 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/796/05796124.pdf [firstpage_image] =>[orig_patent_app_number] => 610070 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/610070
MOS gate controlled thyristor Feb 28, 1996 Issued
Array ( [id] => 3734925 [patent_doc_number] => 05635743 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-03 [patent_title] => 'Semiconductor device having an increased withstand voltage against an inverse surge voltage' [patent_app_type] => 1 [patent_app_number] => 8/604295 [patent_app_country] => US [patent_app_date] => 1996-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2269 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/635/05635743.pdf [firstpage_image] =>[orig_patent_app_number] => 604295 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/604295
Semiconductor device having an increased withstand voltage against an inverse surge voltage Feb 20, 1996 Issued
Array ( [id] => 4161436 [patent_doc_number] => 06104060 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Cost savings for manufacturing planar MOSFET devices achieved by implementing an improved device structure and fabrication process eliminating passivation layer and/or field plate' [patent_app_type] => 1 [patent_app_number] => 8/603638 [patent_app_country] => US [patent_app_date] => 1996-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 4291 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/104/06104060.pdf [firstpage_image] =>[orig_patent_app_number] => 603638 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/603638
Cost savings for manufacturing planar MOSFET devices achieved by implementing an improved device structure and fabrication process eliminating passivation layer and/or field plate Feb 19, 1996 Issued
Array ( [id] => 3931645 [patent_doc_number] => 05952685 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Signal processing applications of massively parallel charge domain computing devices' [patent_app_type] => 1 [patent_app_number] => 8/598900 [patent_app_country] => US [patent_app_date] => 1996-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 6446 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/952/05952685.pdf [firstpage_image] =>[orig_patent_app_number] => 598900 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/598900
Signal processing applications of massively parallel charge domain computing devices Feb 8, 1996 Issued
08/595574 ELECTRONIC DEVICE WITH THIN FILM TRANSISTOR HAVING OHMIC CONTACT LAYERS INTERPOSED BETWEEN SEMICONDUCTOR ACTIVE LAYER AND EACH OF SOURCE AND DRAIN ELECTRODES Jan 31, 1996 Abandoned
Array ( [id] => 3728229 [patent_doc_number] => 05672900 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-30 [patent_title] => 'Insulated gate field effect transistor with an anodic oxidized gate electrode' [patent_app_type] => 1 [patent_app_number] => 8/588677 [patent_app_country] => US [patent_app_date] => 1996-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 2581 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/672/05672900.pdf [firstpage_image] =>[orig_patent_app_number] => 588677 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/588677
Insulated gate field effect transistor with an anodic oxidized gate electrode Jan 18, 1996 Issued
Array ( [id] => 3633313 [patent_doc_number] => 05686756 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-11 [patent_title] => 'Compound field effect transistor having a conductive layer comprising a III-V group compound' [patent_app_type] => 1 [patent_app_number] => 8/587386 [patent_app_country] => US [patent_app_date] => 1996-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3828 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/686/05686756.pdf [firstpage_image] =>[orig_patent_app_number] => 587386 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/587386
Compound field effect transistor having a conductive layer comprising a III-V group compound Jan 16, 1996 Issued
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