| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 3500824
[patent_doc_number] => 05532511
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-02
[patent_title] => 'Semiconductor device comprising a highspeed static induction transistor'
[patent_app_type] => 1
[patent_app_number] => 8/409684
[patent_app_country] => US
[patent_app_date] => 1995-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 24
[patent_no_of_words] => 6275
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/532/05532511.pdf
[firstpage_image] =>[orig_patent_app_number] => 409684
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/409684 | Semiconductor device comprising a highspeed static induction transistor | Mar 22, 1995 | Issued |
Array
(
[id] => 1271300
[patent_doc_number] => RE038296
[patent_country] => US
[patent_kind] => E1
[patent_issue_date] => 2003-11-04
[patent_title] => 'Semiconductor memory device with recessed array region'
[patent_app_type] => E1
[patent_app_number] => 08/408788
[patent_app_country] => US
[patent_app_date] => 1995-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 30
[patent_no_of_words] => 15955
[patent_no_of_claims] => 44
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/RE/038/RE038296.pdf
[firstpage_image] =>[orig_patent_app_number] => 08408788
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/408788 | Semiconductor memory device with recessed array region | Mar 22, 1995 | Issued |
Array
(
[id] => 3626160
[patent_doc_number] => 05689130
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-11-18
[patent_title] => 'Vertical semiconductor device with ground surface providing a reduced ON resistance'
[patent_app_type] => 1
[patent_app_number] => 8/409900
[patent_app_country] => US
[patent_app_date] => 1995-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 17
[patent_no_of_words] => 3626
[patent_no_of_claims] => 51
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/689/05689130.pdf
[firstpage_image] =>[orig_patent_app_number] => 409900
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/409900 | Vertical semiconductor device with ground surface providing a reduced ON resistance | Mar 21, 1995 | Issued |
Array
(
[id] => 3529003
[patent_doc_number] => 05528063
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-06-18
[patent_title] => 'Conductive-overlaid self-aligned MOS-gated semiconductor devices'
[patent_app_type] => 1
[patent_app_number] => 8/409615
[patent_app_country] => US
[patent_app_date] => 1995-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 46
[patent_no_of_words] => 5930
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/528/05528063.pdf
[firstpage_image] =>[orig_patent_app_number] => 409615
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/409615 | Conductive-overlaid self-aligned MOS-gated semiconductor devices | Mar 21, 1995 | Issued |
Array
(
[id] => 3627457
[patent_doc_number] => 05612552
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-03-18
[patent_title] => 'Multilevel gate array integrated circuit structure with perpendicular access to all active device regions'
[patent_app_type] => 1
[patent_app_number] => 8/408035
[patent_app_country] => US
[patent_app_date] => 1995-03-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 25
[patent_no_of_words] => 6498
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 232
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/612/05612552.pdf
[firstpage_image] =>[orig_patent_app_number] => 408035
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/408035 | Multilevel gate array integrated circuit structure with perpendicular access to all active device regions | Mar 20, 1995 | Issued |
Array
(
[id] => 4319615
[patent_doc_number] => 06242777
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-06-05
[patent_title] => 'Field effect transistor and liquid crystal devices including the same'
[patent_app_type] => 1
[patent_app_number] => 8/402374
[patent_app_country] => US
[patent_app_date] => 1995-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 26
[patent_no_of_words] => 5183
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/242/06242777.pdf
[firstpage_image] =>[orig_patent_app_number] => 402374
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/402374 | Field effect transistor and liquid crystal devices including the same | Mar 12, 1995 | Issued |
Array
(
[id] => 3736137
[patent_doc_number] => 05693969
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-02
[patent_title] => 'MESFET having a termination layer in the channel layer'
[patent_app_type] => 1
[patent_app_number] => 8/398838
[patent_app_country] => US
[patent_app_date] => 1995-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 2091
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/693/05693969.pdf
[firstpage_image] =>[orig_patent_app_number] => 398838
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/398838 | MESFET having a termination layer in the channel layer | Mar 5, 1995 | Issued |
| 08/396056 | ARRAY OF THIN FILM TRANSISTORS WITHOUT A STEP REGION AT INTERSECTION OF GATE BUS AND SOURCE BUS ELECTRODES | Feb 27, 1995 | Abandoned |
Array
(
[id] => 3729793
[patent_doc_number] => 05701018
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-23
[patent_title] => 'Semiconductor device having parallel connection of an insulated gate bipolar transistor and a diode'
[patent_app_type] => 1
[patent_app_number] => 8/391568
[patent_app_country] => US
[patent_app_date] => 1995-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 12
[patent_no_of_words] => 5259
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/701/05701018.pdf
[firstpage_image] =>[orig_patent_app_number] => 391568
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/391568 | Semiconductor device having parallel connection of an insulated gate bipolar transistor and a diode | Feb 20, 1995 | Issued |
| 08/391694 | INTEGRATED SEMICONDUCTOR DEVICE | Feb 15, 1995 | Abandoned |
Array
(
[id] => 3496288
[patent_doc_number] => 05561316
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-01
[patent_title] => 'Epitaxial silicon starting material'
[patent_app_type] => 1
[patent_app_number] => 8/389610
[patent_app_country] => US
[patent_app_date] => 1995-02-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1129
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/561/05561316.pdf
[firstpage_image] =>[orig_patent_app_number] => 389610
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/389610 | Epitaxial silicon starting material | Feb 13, 1995 | Issued |
Array
(
[id] => 4422671
[patent_doc_number] => 06194773
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-27
[patent_title] => 'Vertical transistor having top and bottom surface isolation'
[patent_app_type] => 1
[patent_app_number] => 8/384816
[patent_app_country] => US
[patent_app_date] => 1995-02-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 1608
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/194/06194773.pdf
[firstpage_image] =>[orig_patent_app_number] => 384816
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/384816 | Vertical transistor having top and bottom surface isolation | Feb 5, 1995 | Issued |
Array
(
[id] => 4038191
[patent_doc_number] => 05994757
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-30
[patent_title] => 'Electronic circuit device capable for use as a memory device'
[patent_app_type] => 1
[patent_app_number] => 8/383186
[patent_app_country] => US
[patent_app_date] => 1995-02-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 17
[patent_no_of_words] => 10592
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/994/05994757.pdf
[firstpage_image] =>[orig_patent_app_number] => 383186
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/383186 | Electronic circuit device capable for use as a memory device | Feb 2, 1995 | Issued |
Array
(
[id] => 3666684
[patent_doc_number] => 05625217
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-04-29
[patent_title] => 'MOS transistor having a composite gate electrode and method of fabrication'
[patent_app_type] => 1
[patent_app_number] => 8/384352
[patent_app_country] => US
[patent_app_date] => 1995-02-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 3574
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 210
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/625/05625217.pdf
[firstpage_image] =>[orig_patent_app_number] => 384352
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/384352 | MOS transistor having a composite gate electrode and method of fabrication | Feb 1, 1995 | Issued |
Array
(
[id] => 3534263
[patent_doc_number] => 05583366
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-10
[patent_title] => 'Active matrix panel'
[patent_app_type] => 1
[patent_app_number] => 8/378906
[patent_app_country] => US
[patent_app_date] => 1995-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 16
[patent_no_of_words] => 5604
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 232
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/583/05583366.pdf
[firstpage_image] =>[orig_patent_app_number] => 378906
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/378906 | Active matrix panel | Jan 25, 1995 | Issued |
| 08/378316 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME | Jan 24, 1995 | Abandoned |
Array
(
[id] => 3551698
[patent_doc_number] => 05545915
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-08-13
[patent_title] => 'Semiconductor device having field limiting ring and a process therefor'
[patent_app_type] => 1
[patent_app_number] => 8/376566
[patent_app_country] => US
[patent_app_date] => 1995-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 4271
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 353
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/545/05545915.pdf
[firstpage_image] =>[orig_patent_app_number] => 376566
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/376566 | Semiconductor device having field limiting ring and a process therefor | Jan 22, 1995 | Issued |
| 08/371385 | FIELD EFFECT TRANSISTOR WITH RECESSED BURIED SOURCE AND DRAIN REGIONS | Jan 10, 1995 | Abandoned |
Array
(
[id] => 3734759
[patent_doc_number] => 05635732
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-06-03
[patent_title] => 'Silicon carbide LOCOS vertical MOSFET device'
[patent_app_type] => 1
[patent_app_number] => 8/370142
[patent_app_country] => US
[patent_app_date] => 1995-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 3297
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 236
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/635/05635732.pdf
[firstpage_image] =>[orig_patent_app_number] => 370142
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/370142 | Silicon carbide LOCOS vertical MOSFET device | Jan 8, 1995 | Issued |
Array
(
[id] => 3529448
[patent_doc_number] => 05504359
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-02
[patent_title] => 'Vertical FET device with low gate to source overlap capacitance'
[patent_app_type] => 1
[patent_app_number] => 8/369851
[patent_app_country] => US
[patent_app_date] => 1995-01-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 11
[patent_no_of_words] => 2203
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/504/05504359.pdf
[firstpage_image] =>[orig_patent_app_number] => 369851
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/369851 | Vertical FET device with low gate to source overlap capacitance | Jan 5, 1995 | Issued |