Search

Devon C. Kramer

Supervisory Patent Examiner (ID: 1983, Phone: (571)272-7118 , Office: P/3746 )

Most Active Art Unit
3683
Art Unit(s)
3683, 3741, 3613, 3746
Total Applications
1035
Issued Applications
672
Pending Applications
81
Abandoned Applications
283

Applications

Application numberTitle of the applicationFiling DateStatus
08/339208 SEMICONDUCTOR DEVICE INCLUDING VERTICAL MOSFET STRUCTURE WITH SUPPRESSED PARASITIC DIODE OPERATION Nov 9, 1994 Abandoned
08/334986 SEMICONDUCTOR DEVICE HAVING A BURIED CHANNEL TRANSISTOR Nov 6, 1994 Abandoned
08/335526 ZENNER DIODES ON THE SAME WAFER WITH BICDMOS STRUCTURES Nov 6, 1994 Abandoned
08/333990 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME Nov 1, 1994 Abandoned
Array ( [id] => 3511259 [patent_doc_number] => 05569957 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-29 [patent_title] => 'Low inductance conductor topography for MOSFET circuit' [patent_app_type] => 1 [patent_app_number] => 8/332300 [patent_app_country] => US [patent_app_date] => 1994-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 11 [patent_no_of_words] => 1936 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/569/05569957.pdf [firstpage_image] =>[orig_patent_app_number] => 332300 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/332300
Low inductance conductor topography for MOSFET circuit Oct 30, 1994 Issued
Array ( [id] => 3732259 [patent_doc_number] => 05652441 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-29 [patent_title] => 'Gate array base cell with novel gate structure' [patent_app_type] => 1 [patent_app_number] => 8/328998 [patent_app_country] => US [patent_app_date] => 1994-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 3286 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/652/05652441.pdf [firstpage_image] =>[orig_patent_app_number] => 328998 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/328998
Gate array base cell with novel gate structure Oct 24, 1994 Issued
Array ( [id] => 3498614 [patent_doc_number] => 05508547 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-16 [patent_title] => 'LDMOS transistor with reduced projective area of source region' [patent_app_type] => 1 [patent_app_number] => 8/324802 [patent_app_country] => US [patent_app_date] => 1994-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 1542 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/508/05508547.pdf [firstpage_image] =>[orig_patent_app_number] => 324802 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/324802
LDMOS transistor with reduced projective area of source region Oct 17, 1994 Issued
Array ( [id] => 3585980 [patent_doc_number] => 05581097 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-03 [patent_title] => 'Method of fabricating semiconductor device using shared contact hole masks and semiconductor device using same' [patent_app_type] => 1 [patent_app_number] => 8/321736 [patent_app_country] => US [patent_app_date] => 1994-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 34 [patent_no_of_words] => 9474 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/581/05581097.pdf [firstpage_image] =>[orig_patent_app_number] => 321736 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/321736
Method of fabricating semiconductor device using shared contact hole masks and semiconductor device using same Oct 11, 1994 Issued
Array ( [id] => 3812233 [patent_doc_number] => 05813168 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-29 [patent_title] => 'Environmentally controlled greenhouse' [patent_app_type] => 1 [patent_app_number] => 8/313186 [patent_app_country] => US [patent_app_date] => 1994-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4560 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/813/05813168.pdf [firstpage_image] =>[orig_patent_app_number] => 313186 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/313186
Environmentally controlled greenhouse Oct 6, 1994 Issued
08/318109 GATE ARRAY TYPE SEMICONDUCTOR DEVICE WITH FLEXIBLE PELLET SIZE Oct 4, 1994 Abandoned
Array ( [id] => 3529476 [patent_doc_number] => 05504361 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-02 [patent_title] => 'Polarity-reversal protection for integrated electronic circuits in CMOS technology' [patent_app_type] => 1 [patent_app_number] => 8/318150 [patent_app_country] => US [patent_app_date] => 1994-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1942 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/504/05504361.pdf [firstpage_image] =>[orig_patent_app_number] => 318150 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/318150
Polarity-reversal protection for integrated electronic circuits in CMOS technology Oct 4, 1994 Issued
Array ( [id] => 3525711 [patent_doc_number] => 05489795 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-06 [patent_title] => 'Semiconductor integrated circuit device having double well structure' [patent_app_type] => 1 [patent_app_number] => 8/317835 [patent_app_country] => US [patent_app_date] => 1994-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 8379 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/489/05489795.pdf [firstpage_image] =>[orig_patent_app_number] => 317835 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/317835
Semiconductor integrated circuit device having double well structure Oct 3, 1994 Issued
Array ( [id] => 3565376 [patent_doc_number] => 05525815 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-11 [patent_title] => 'Diamond film structure with high thermal conductivity' [patent_app_type] => 1 [patent_app_number] => 8/316998 [patent_app_country] => US [patent_app_date] => 1994-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2771 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/525/05525815.pdf [firstpage_image] =>[orig_patent_app_number] => 316998 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/316998
Diamond film structure with high thermal conductivity Oct 2, 1994 Issued
08/316166 BIPOLAR TRANSISTOR FOR USE IN LINEAR AMPLIFIERS HAVING REDUCED HARMONIC DISTORTION AND METHOD OF FABRICATION Sep 29, 1994 Abandoned
Array ( [id] => 3498716 [patent_doc_number] => 05508552 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-16 [patent_title] => 'Transistors with multiple emitters, and transistors with substantially square base emitter junctions' [patent_app_type] => 1 [patent_app_number] => 8/315731 [patent_app_country] => US [patent_app_date] => 1994-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 4754 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/508/05508552.pdf [firstpage_image] =>[orig_patent_app_number] => 315731 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/315731
Transistors with multiple emitters, and transistors with substantially square base emitter junctions Sep 29, 1994 Issued
Array ( [id] => 3486971 [patent_doc_number] => 05446304 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-29 [patent_title] => 'Insulated-gate-type field effect transistor which has subgates that have different spacing from the substrate than the main gate' [patent_app_type] => 1 [patent_app_number] => 8/314929 [patent_app_country] => US [patent_app_date] => 1994-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 4055 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/446/05446304.pdf [firstpage_image] =>[orig_patent_app_number] => 314929 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/314929
Insulated-gate-type field effect transistor which has subgates that have different spacing from the substrate than the main gate Sep 28, 1994 Issued
08/314860 LOW COLLECTOR RESISTANCE BIPOLAR TRANSISTOR COMPATIBLE WITH HIGH VOLTAGE INTEGRATED CIRCUITS Sep 28, 1994 Abandoned
Array ( [id] => 3461722 [patent_doc_number] => 05473191 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-05 [patent_title] => 'Hybrid integrated circuit device with apertured cover' [patent_app_type] => 1 [patent_app_number] => 8/314620 [patent_app_country] => US [patent_app_date] => 1994-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 3267 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/473/05473191.pdf [firstpage_image] =>[orig_patent_app_number] => 314620 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/314620
Hybrid integrated circuit device with apertured cover Sep 28, 1994 Issued
08/313628 ELECTRICALLY CONDUCTIVE SUBSTRATE INTERCONNECT CONTINUITY REGION AND METHOD OF FORMING SAME WITH AN ANGLED IMPLANT Sep 26, 1994 Abandoned
Array ( [id] => 3627865 [patent_doc_number] => 05602417 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-11 [patent_title] => 'Low-noise bipolar transistor operating predominantly in the bulk region' [patent_app_type] => 1 [patent_app_number] => 8/312386 [patent_app_country] => US [patent_app_date] => 1994-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 12 [patent_no_of_words] => 3181 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/602/05602417.pdf [firstpage_image] =>[orig_patent_app_number] => 312386 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/312386
Low-noise bipolar transistor operating predominantly in the bulk region Sep 25, 1994 Issued
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