| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 3802190
[patent_doc_number] => 05828124
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-27
[patent_title] => 'Low-noise bipolar transistor'
[patent_app_type] => 1
[patent_app_number] => 8/312472
[patent_app_country] => US
[patent_app_date] => 1994-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 2669
[patent_no_of_claims] => 15
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/828/05828124.pdf
[firstpage_image] =>[orig_patent_app_number] => 312472
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/312472 | Low-noise bipolar transistor | Sep 25, 1994 | Issued |
| 08/310814 | FET HAVING PART OF ACTIVE REGION FORMED IN SEMICONDUCTOR LAYER IN THROUGH HOLE FORMED IN GATE ELECTRODE AND METHOD FOR MANUCTURING THE SAME | Sep 21, 1994 | Abandoned |
Array
(
[id] => 3553328
[patent_doc_number] => 05548133
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-08-20
[patent_title] => 'IGBT with increased ruggedness'
[patent_app_type] => 1
[patent_app_number] => 8/308556
[patent_app_country] => US
[patent_app_date] => 1994-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 2567
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 273
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/548/05548133.pdf
[firstpage_image] =>[orig_patent_app_number] => 308556
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/308556 | IGBT with increased ruggedness | Sep 18, 1994 | Issued |
| 08/303622 | SEMICONDUCTOR DEVICE IN A THIN ACTIVE LAYER WITH HIGH BREAKDOWN VOLTAGE | Sep 8, 1994 | Abandoned |
Array
(
[id] => 3671773
[patent_doc_number] => 05600156
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-02-04
[patent_title] => 'Diamond semiconductor device with P-I-N type multilayer structure'
[patent_app_type] => 1
[patent_app_number] => 8/303112
[patent_app_country] => US
[patent_app_date] => 1994-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 33
[patent_no_of_words] => 11790
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/600/05600156.pdf
[firstpage_image] =>[orig_patent_app_number] => 303112
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/303112 | Diamond semiconductor device with P-I-N type multilayer structure | Sep 7, 1994 | Issued |
Array
(
[id] => 3593051
[patent_doc_number] => 05497014
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-03-05
[patent_title] => 'BI-CMOS gate array semiconductor integrated circuits and internal cell structure involved in the same'
[patent_app_type] => 1
[patent_app_number] => 8/300132
[patent_app_country] => US
[patent_app_date] => 1994-09-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 7145
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/497/05497014.pdf
[firstpage_image] =>[orig_patent_app_number] => 300132
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/300132 | BI-CMOS gate array semiconductor integrated circuits and internal cell structure involved in the same | Sep 1, 1994 | Issued |
| 08/300476 | SEMICONDUCTOR HAVING SELECTIVELY ENHANCED FIELD OXIDE AREAS AND METHOD FOR PRODUCING SAME | Sep 1, 1994 | Abandoned |
Array
(
[id] => 3592154
[patent_doc_number] => 05550397
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-08-27
[patent_title] => 'Metal oxide semiconductor transistors having a polysilicon gate electrode with nonuniform doping in source-drain direction'
[patent_app_type] => 1
[patent_app_number] => 8/299855
[patent_app_country] => US
[patent_app_date] => 1994-09-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 2322
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 215
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/550/05550397.pdf
[firstpage_image] =>[orig_patent_app_number] => 299855
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/299855 | Metal oxide semiconductor transistors having a polysilicon gate electrode with nonuniform doping in source-drain direction | Aug 31, 1994 | Issued |
Array
(
[id] => 3585950
[patent_doc_number] => 05581095
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-03
[patent_title] => 'Bidirectional shockley diode having overlapping emitter regions'
[patent_app_type] => 1
[patent_app_number] => 8/298074
[patent_app_country] => US
[patent_app_date] => 1994-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 1980
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 150
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/581/05581095.pdf
[firstpage_image] =>[orig_patent_app_number] => 298074
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/298074 | Bidirectional shockley diode having overlapping emitter regions | Aug 29, 1994 | Issued |
Array
(
[id] => 3586023
[patent_doc_number] => 05581100
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-03
[patent_title] => 'Trench depletion MOSFET'
[patent_app_type] => 1
[patent_app_number] => 8/298462
[patent_app_country] => US
[patent_app_date] => 1994-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 19
[patent_no_of_words] => 2963
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 303
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/581/05581100.pdf
[firstpage_image] =>[orig_patent_app_number] => 298462
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/298462 | Trench depletion MOSFET | Aug 29, 1994 | Issued |
Array
(
[id] => 3627581
[patent_doc_number] => 05612559
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-03-18
[patent_title] => 'Semiconductor device having pillar shaped transistor and a method for manufacturing the same'
[patent_app_type] => 1
[patent_app_number] => 8/298470
[patent_app_country] => US
[patent_app_date] => 1994-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 27
[patent_no_of_words] => 4346
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/612/05612559.pdf
[firstpage_image] =>[orig_patent_app_number] => 298470
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/298470 | Semiconductor device having pillar shaped transistor and a method for manufacturing the same | Aug 29, 1994 | Issued |
| 08/296294 | MOS TRANSISTOR HAVING INCREASED GATE-DRAIN CAPACITANCE | Aug 24, 1994 | Abandoned |
| 08/291496 | SEMICONDUCTOR DEVICE HAVING CMOS CIRCUIT | Aug 16, 1994 | Abandoned |
Array
(
[id] => 3523820
[patent_doc_number] => 05530263
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-06-25
[patent_title] => 'Three dot computing elements'
[patent_app_type] => 1
[patent_app_number] => 8/291306
[patent_app_country] => US
[patent_app_date] => 1994-08-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 2466
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/530/05530263.pdf
[firstpage_image] =>[orig_patent_app_number] => 291306
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/291306 | Three dot computing elements | Aug 15, 1994 | Issued |
| 08/288685 | HIGH POWER MOSFET WITH LOW ON-RESISTANCE AND HIGH BREAKDOWN VOLTAGE | Aug 10, 1994 | Abandoned |
| 08/289365 | INTEGRATED CIRCUIT STRUCTURE AND METHOD OF FABRICATION THEREOF | Aug 10, 1994 | Abandoned |
Array
(
[id] => 3865555
[patent_doc_number] => 05796129
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-18
[patent_title] => 'Master slice type integrated circuit system having block areas optimized based on function'
[patent_app_type] => 1
[patent_app_number] => 8/283766
[patent_app_country] => US
[patent_app_date] => 1994-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 21
[patent_no_of_words] => 8629
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 346
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/796/05796129.pdf
[firstpage_image] =>[orig_patent_app_number] => 283766
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/283766 | Master slice type integrated circuit system having block areas optimized based on function | Jul 31, 1994 | Issued |
| 08/273166 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME | Jul 24, 1994 | Abandoned |
Array
(
[id] => 3496159
[patent_doc_number] => 05561307
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-01
[patent_title] => 'Ferroelectric integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 8/276474
[patent_app_country] => US
[patent_app_date] => 1994-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 20
[patent_no_of_words] => 9659
[patent_no_of_claims] => 9
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/561/05561307.pdf
[firstpage_image] =>[orig_patent_app_number] => 276474
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/276474 | Ferroelectric integrated circuit | Jul 17, 1994 | Issued |
Array
(
[id] => 3559269
[patent_doc_number] => 05543653
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-08-06
[patent_title] => 'Bipolar and BiCMOS structures'
[patent_app_type] => 1
[patent_app_number] => 8/275062
[patent_app_country] => US
[patent_app_date] => 1994-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 17
[patent_no_of_words] => 5777
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/543/05543653.pdf
[firstpage_image] =>[orig_patent_app_number] => 275062
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/275062 | Bipolar and BiCMOS structures | Jul 12, 1994 | Issued |